Preamble detection circuit for digital communications system

Claim 2

A preamble detection circuit for a transmission system in which a preamble and a digital signal are modulated upon orthogonal carriers and transmitted in a series of burst signals said preamble containing a predetermined bit pattern, comprising: orthogonal demodulator means for receiving the transmitted burst signals and noncoherently detecting the preamble and the digital signal with local orthogonal carriers having the same frequency as the frequency of the transmitted orthogonal carriers, said local orthogonal carriers tending to deviate in phase over a predetermined range from the transmitted orthogonal carriers, said orthogonal demodulator means generating in-phase and quadrature output signals; means for generating a local bit pattern corresponding to the bit pattern contained in said preamble; first and second correlators, the first correlator providing a correlation calculation between the local bit pattern and the in-phase output signal and the second correlator providing a correlation calculation between the local bit pattern and the quadrature output signal; carrier phase error detector means connected to the outputs of the first and second correlators for detecting a phase error of the local orthogonal carriers with respect to the transmitted carriers; symbol clock generator means for generating a local clock pulse at a symbol rate of the transmitted burst signals; and clock phase error detector means connected to one of the outputs of the first and second correlators and to the output of the symbol clock generator means for detecting a phase error of the local clock pulse with respect to symbols contained in the transmitted burst signals and controlling the symbol clock generator means with the detected phase error.

Claim 3

A preamble detection circuit as claimed in claim 1, further comprising power level detector means connected to the outputs of the first and second correlators for detecting a power level of the received burst signals.

Claim 4

A preamble detection circuit in claim 1 or 2, wherein the bit pattern contained in the preamble is a series of alternating binary logic values.

Claim 5

A preamble detection circuit as claimed in any one of claims 1 to 3, wherein the carrier phase error detector means comprises: a division circuit for providing a division calculation between the in-­phase and quadrature output signals to produce a quotient; and arctangent calculator means for determining the arctangent of the quotient.

Claim 6

A preamble detection circuit as claimed in any one of claims 1 to 4, wherein the clock phase error detector means comprises: delay means for delaying the local clock pulse by an amount corresponding to one-half the interval between successive symbols contained in the transmitted burst signals; first sampling means for sampling one of the in-phase and quadrature output signals in response to the delayed local clock pulse; second sampling means for sampling the one of said in-phase and quadrature output signals in response to the local clock pulse; symbol detector means for detecting a predetermined symbol from the output of the second sampling means; and multiplier means for generating a signal representative of a product of the output of the first sampling means and the predetermined symbol.

Claim 7

A digital communication system in which a preamble and a digital signal are modulated upon orthogonal carriers and transmitted to a distant end of the system in a series of burst signals, the preamble containing a predetermined bit pattern for carrier and clock recovery at the distant end of the system, comprising at the distant end: gain-controlled amplifier means for receiving the transmitted burst signals and amplifying the received signals; orthogonal demodulator means connected to the amplifier means for noncoherently detecting the preamble and the digital signal with local orthogonal carriers having the same frequency as the frequency of the transmitted orthogonal carriers, said local orthogonal carriers tending to deviate in phase over a predetermined range from the transmitted orthogonal carriers, said orthogonal demodulator means generating in-­phase and quadrature output signals; means for generating a local bit pattern corresponding to the bit pattern contained in said preamble; first and second correlators, the first correlator providing a correlation calculation between the local bit pattern and the in-phase output signal and the second correlator providing a correlation calculation between the local bit pattern and the quadrature output signal; symbol clock generator means for generating a local clock pulse at a symbol rate of the transmitted burst signals; first and second decision circuits responsive to the local clock pulse for respectively sampling the in-phase and quadrature output signals; clock phase error detector means connected to one of the outputs of the first and second correlators and to the output of the symbol clock generator means for detecting a phase error of the local clock pulse with respect to symbols contained in the transmitted burst signals and controlling the symbol clock generator means with the detected phase error; carrier generator means for generating second local orthogonal carriers; synchronous detector means for providing synchronous detection on output signals from the first and second decision circuits with the second local orthogonal carriers; carrier phase error detector means connected to the outputs of the first and second correlators for detecting a phase error of the local orthogonal carriers with respect to the transmitted carriers and controlling the carrier generator means with the detected phase error; and power level detector means connected to the outputs of the first and second correlators for detecting a power level of the received burst signals and controlling the gain-controlled amplifier means with the detected power level.

Claim 8

A digital communication system in which a preamble and a digital signal are modulated upon orthogonal carriers and transmitted to a distant end of the system in a series of burst signals, the preamble containing a predetermined bit pattern for carrier and clock recovery at the distant end of the system, comprising at the distant end: gain-controlled amplifier means for receiving the transmitted burst signals and amplifying the received signals; orthogonal demodulator means connected to the amplifier means for noncoherently detecting the preamble and the digital signal with local orthogonal carriers having the same frequency as the frequency of the transmitted orthogonal carriers, said local orthogonal carriers tending to deviate in phase over a predetermined range from the transmitted orthogonal carriers, said orthogonal demodulator means generating in-­phase and quadrature output signals; means for generating a local bit pattern corresponding to the bit pattern contained in said preamble; first and second correlators, the first correlator providing a correlation calculation between the local bit pattern and the in-phase output signal and the second correlator providing a correlation calculation between the local bit pattern and the quadrature output signal; symbol clock generator means for generating a local clock pulse at a symbol rate of the transmitted burst signals; first and second decision circuits responsive to the local clock pulse for respectively sampling the in-phase and quadrature output signals; clock phase error detector means connected to one of the outputs of the first and second correlators and to the output of the symbol clock generator means for detecting a phase error of the local clock pulse with respect to symbols contained in the transmitted burst signals and controlling the symbol clock generator means with the detected phase error; carrier generator means for generating second local orthogonal carriers; synchronous detector means for providing synchronous detection on output signals from the first and second decision circuits with the second local orthogonal carriers; carrier phase error detector means connected to the outputs of the first and second correlators for detecting a phase error of the local orthogonal carriers with respect to the transmitted carriers and controlling the carrier generator means with the detected phase error; and power level detector means connected to the outputs of the first and second correlators for detecting a power level of the received burst signals and controlling the gain-controlled amplifier means with the detected power level.

Claim 9

A digital communication system as claimed in claim 6, wherein the bit pattern contained in the preamble is a series of alternating binary logic values.

Claim 10

A digital communication system as claimed in claim 6 or 7, wherein the carrier phase error detector means comprises: a division circuit for providing a division calculation between the in-­phase and quadrature output signals to produce a quotient; and arctangent calculator means for determining the arctangent of the quotient.

Claim 11

A digital communication system as claimed in any one of claims 6 to 8, wherein the clock phase error detector means comprises: delay means for delaying the local clock pulse by an amount corresponding to one-half the interval between successive symbols contained in the transmitted burst signals; first sampling means for sampling one of the in-phase and quadrature output signals in response to the delayed local clock pulse; second sampling means for sampling the one of said in-phase and quadrature output signals in response to the local clock pulse; symbol detector means for detecting a predetermined symbol from the output of the second sampling means; and multiplier means for generating a signal representative of a product of the output of the first sampling means and the predetermined symbol.

Claim 12

A digital communication system as claimed in any one of claims 6 to 9, further comprising means for sampling the detected power level in response to the local clock pulse and supplying the sampled power level to the gain-­controlled amplifier means as said detected power level.