Patent EP0354740A2 successfully refreshed from Google Patents.
EP0354740A2
Expired / Lapsed
EP
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Data processing apparatus for performing parallel decoding and parallel execution of a variable word length instruction
Assignee: Panasonic Holdings Corp
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Filing: 1989-08-04
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Granted: —
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Expires: 2009-08-04
Abstract
Abstract A data processing apparatus for decoding and executing instructions in a parallel manner in a variable word length instruction format. A plurality of decoders is used in which while the primary instruction decoder (12) is decoding an instruction, the probability of parallel decoding of the next instruction is detected, so that the primary instruction decoder and a secondary instruction decoder (13) decode a variable word length instruction and a fixed word length instruction, respectively, in a parallel manner. A conditional branch instruction of a fixed word length and the subsequent instruction of a variable word length are decoded and executed in a parallel manner to increase the speed at which the conditional branch instruction is executed.
Inventors
- 👤 Toshimichi Matsuzaki
- 👤 Takashi Sakao
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-04 14:26
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3802; G06F9/3804; G06F9/30145; G06F9/30149; G06F9/30152; G06F9/3818; G06F9/3822; G06F9/3836; G06F9/3842
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
157 words
A data processing apparatus comprising: a first instruction decoder (12) for decoding a variable word length instruction; parallel decoding probability detection means (21) for decoding the instruction word subsequent to the instruction decoded by the first instruction decoder (12) and for beforehand detecting the presence of instructions decodable in a parallel manner; at least one second instruction decoder (13) for decoding the instruction detected by the parallel decoding probability detection means (21); and instruction supplying means (19) for selectively validating the instruction detected by the parallel decoding probability detection means (21) in accordance with a signal indicative of the boundary of the instruction outputted by the first instruction decoder (12), supplying the validated instruction to the second instruction decoder (13) and the instruction subsequent to the former instruction to the first instruction decoder (12) whereby the plurality of instructions including at least one fixed length instruction in a variable instruction format are decoded in a parallel manner.
Claim 2
Dependent Claim
157 words
A data processing apparatus comprising: a first instruction decoder (12) for decoding a variable word length instruction; parallel decoding probability detection means (21) for decoding the instruction word subsequent to the instruction decoded by the first instruction decoder (12) and for beforehand detecting the presence of instructions decodable in a parallel manner; at least one second instruction decoder (13) for decoding the instruction detected by the parallel decoding probability detection means (21); and instruction supplying means (19) for selectively validating the instruction detected by the parallel decoding probability detection means (21) in accordance with a signal indicative of the boundary of the instruction outputted by the first instruction decoder (12), supplying the validated instruction to the second instruction decoder (13) and the instruction subsequent to the former instruction to the first instruction decoder (12) whereby the plurality of instructions including at least one fixed length instruction in a variable instruction format are decoded in a parallel manner.
Claim 3
Dependent Claim
212 words
A data processing apparatus comprising: a first instruction decoder (12) for decoding a variable word length instruction; parallel decoding probability detection means (21) for decoding the instruction word subsequent to the instruction decoded by the first instruction decoder (12) and for beforehand detecting the presence of instructions decodable in a parallel manner; at least one second instruction decoder (13) for decoding the instruction detected by the parallel decoding probability detection means (21); instruction supplying means (19) for selectively validating the instruction detected by the parallel decoding probability detection means (21) in accordance with a signal indicative of the boundary of the instruction outputted by the first instruction decoder (12), supplying the validated instruction to the second instruction decoder (13) and the instruction subsequent to the former instruction to the first instruction decoder (12); an adder (30) for calculating a branch target address of a conditional branch instruction; a comparator (27) for detecting whether conditions are met; and branch control means (26) for suppressing the execution of the instructions subsequent to the conditional branch instruction only when the conditions are met and for starting the execution of the instruction from the branch target address outputted by the adder (30), whereby the conditional branch instruction and subsequent instructions are processed in a parallel manner.
Claim 4
Dependent Claim
212 words
A data processing apparatus comprising: a first instruction decoder (12) for decoding a variable word length instruction; parallel decoding probability detection means (21) for decoding the instruction word subsequent to the instruction decoded by the first instruction decoder (12) and for beforehand detecting the presence of instructions decodable in a parallel manner; at least one second instruction decoder (13) for decoding the instruction detected by the parallel decoding probability detection means (21); instruction supplying means (19) for selectively validating the instruction detected by the parallel decoding probability detection means (21) in accordance with a signal indicative of the boundary of the instruction outputted by the first instruction decoder (12), supplying the validated instruction to the second instruction decoder (13) and the instruction subsequent to the former instruction to the first instruction decoder (12); an adder (30) for calculating a branch target address of a conditional branch instruction; a comparator (27) for detecting whether conditions are met; and branch control means (26) for suppressing the execution of the instructions subsequent to the conditional branch instruction only when the conditions are met and for starting the execution of the instruction from the branch target address outputted by the adder (30), whereby the conditional branch instruction and subsequent instructions are processed in a parallel manner.
Claim 5
Dependent Claim
216 words
A data processing apparatus comprising: a first instruction decoder (12) for decoding a variable word length instruction; parallel decoding probability detection means (21) for decoding the instruction word subsequent to the instruction decoded by the first instruction decoder (12) and for beforehand detecting the presence of instructions decodable in a parallel manner; at least one second instruction decoder (13) for decoding the instruction detected by the parallel decoding probability detection means (21); instruction supplying means (19) for selectively validating the instruction detected by the parallel decoding probability detection means (21) in accordance with a signal indicative of the boundary of the instruction outputted by the first instruction decoder (12), supplying the validated instruction to the second instruction decoder (13) and the instruction subsequent to the former instruction to the first instruction decoder (12); means (21) for reading a memory; means (24) for performing a calculation among a plurality of registers; means (31) for delaying the operation of the calculation performing means using the results of the decoding by the first and second instruction decoders (12, 13); and means (25) for writing data into the memory, whereby an instruction for transfer of data in the memory and the internal register and the instructions subsequent to the instruction for transfer of data are processed in a parallel manner.
Claim 6
Dependent Claim
216 words
A data processing apparatus comprising: a first instruction decoder (12) for decoding a variable word length instruction; parallel decoding probability detection means (21) for decoding the instruction word subsequent to the instruction decoded by the first instruction decoder (12) and for beforehand detecting the presence of instructions decodable in a parallel manner; at least one second instruction decoder (13) for decoding the instruction detected by the parallel decoding probability detection means (21); instruction supplying means (19) for selectively validating the instruction detected by the parallel decoding probability detection means (21) in accordance with a signal indicative of the boundary of the instruction outputted by the first instruction decoder (12), supplying the validated instruction to the second instruction decoder (13) and the instruction subsequent to the former instruction to the first instruction decoder (12); means (21) for reading a memory; means (24) for performing a calculation among a plurality of registers; means (31) for delaying the operation of the calculation performing means using the results of the decoding by the first and second instruction decoders (12, 13); and means (25) for writing data into the memory, whereby an instruction for transfer of data in the memory and the internal register and the instructions subsequent to the instruction for transfer of data are processed in a parallel manner.
References Cited (Backward Citations)
JPS6349843A
Cited
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