Power saving arrangement and power saving method

Claim 1

A power saving arrangement for use in a subsidiary unit which communicates with a base unit in response to the detection of an ID signal leading data signal which are produced from said base unit and received by said subsidiary unit, said power saving arrangement comprising: a power control circuit (23, 24) for selectively producing a full power and a reduced power; a processing circuit means (12, 13, 14, 15, 18) for receiving and processing said data signal when the full power is applied thereto, and for detecting the level of the received signal when the reduced electric power is applied thereto; detecting circuit means (16, 17), connected to said processing circuit means, for detecting data signal when the full power is applied thereto, and for detecting only the ID signal when the reduced power is applied thereto; first and second switching means (SW1, SW2, SW3) for making and breaking a power supply path to said detecting circuit means from said power control circuit; and control means (CPU) for controlling said power control circuit and said first switching means to establish either one of first standby mode, second standby mode and use mode such that: in the first standby mode, said first and second switching means (SW1, SW2, SW3) break the power supply to said detecting circuit means (16, 17) and, at the same time, the power control circuit (23, 24) produces the reduced power to said processing circuit means (12, 13, 14, 15, 18), ready to detect the level of the received signal; in the second standby mode as established when said control means (CPU) detects that the received signal level exceeds a predetermined level, said first and second switching means (SW1, SW2, SW3) make the power supply to said detecting circuit means (16, 17) and, at the same time, the power control circuit (23, 24) produces the reduced power to said processing circuit means and also to said detecting circuit means, ready to detect and read the pattern of said ID signal; and in the use mode as established when said control means (CPU) detects that said ID signal has a predetermined pattern, said first and second switching means (SW1, SW2, SW3) make the power supply to said detecting circuit means (16, 17) and, at the same time, the power control circuit (23, 24) produces the full power to said processing circuit means (12, 13, 14, 15, 18) and also to said detecting circuit means (16, 17), ready to detect and read said data signal.