Patent EP0361609A2 successfully refreshed from Google Patents.
EP0361609A2
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EP
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Thin-film transistors, their method of manufacture, and display device using such transistors
Assignee: Philips Electronics UK Ltd
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Filing: 1989-09-25
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Granted: —
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Expires: 2009-09-25
Abstract
Abstract A TFT is fabricated by providing on a substrate (10), and over a gate (12), a sequentially formed multi-layer structure consisting of a gate insulator layer (14), an intrinsic semiconductor, e.g. a-Si or polysilicon, layer (16) for the channel, a doped semiconductor, e.g. n type a-Si or polysilicon, layer (18) for source and drain contact regions and a passivating layer (20). The layer (18) extends completely over and covers the channel region of the layer (16). Thereafter, the portion (30) of layer (18) overlying the channel region is converted by a compensating doping implant to a highly resistive form separating the source and drain contact regions, and windows (22, 24) are defined in the passivating layer (20) into which source and drain contacts (26, 28) are deposited. In this way critical interfaces are protected from contamination. The TFT is suitable for use as a switching element in active matrix display devices, e.g. LC-TVs.
Inventors
- 👤 Keith Harlow Nicholas
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-03 05:24
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/031; H10D30/0312; H10D30/0316; H10D10/00; H10D10/01; G; G02; G02F; G02F1/00; G02F1/01; G02F1/13; G02F1/133; G02F1/136; G02F1/1362; G02F1/1368; H10D30/0321; H10D30/60; H10D30/67; H10D30/6729; H10D30/673; H10D30/6732; H10D30/674; H10D30/6741; H10D30/6743; H10D30/6746; G02F2202/00; G02F2202/10; G02F2202/103; G02F2202/104; Y; Y10; Y10S; Y10S148/00; Y10S148/018; Y10S148/105; Y10S438/00; Y10S438/914; Y10S438/919
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
115 words
A method of fabricating a TFT comprising the steps of forming on a substrate carrying a gate electrode, a multi-layer structure comprising, in superimposed relationship, a gate insulator layer, an intrinsic semiconductor layer which is to provide a channel, a doped semiconductor layer which is to form source and drain contact regions and a passivating layer, characterised in that the doped semiconductor layer is provided in the multi-layer structure as a layer extending over the channel region of the intrinsic semiconductor layer and in that a portion of the doped semiconductor layer overlying said region is subsequently converted into a highly resistive portion which separates the source and drain contact forming regions of that layer.
Claim 2
Independent Claim
115 words
A method of fabricating a TFT comprising the steps of forming on a substrate carrying a gate electrode, a multi-layer structure comprising, in superimposed relationship, a gate insulator layer, an intrinsic semiconductor layer which is to provide a channel, a doped semiconductor layer which is to form source and drain contact regions and a passivating layer, characterised in that the doped semiconductor layer is provided in the multi-layer structure as a layer extending over the channel region of the intrinsic semiconductor layer and in that a portion of the doped semiconductor layer overlying said region is subsequently converted into a highly resistive portion which separates the source and drain contact forming regions of that layer.
Claim 3
Dependent Claim
23 words
A method according to Claim 1, characterised in that the semiconductor material used for the intrinsic and doped semiconductor layers comprises amorphous silicon.
Claim 4
Dependent Claim
22 words
A method according to Claim 1, characterised in that the semiconductor material used for the intrinsic and doped semiconductor layers comprises polysilicon.
Claim 5
Independent Claim
33 words
A method according to any one of the preceding claims, characterised in that the said region of the doped semiconductor layer is converted to a high resistance region by a compensating doping implant.
Claim 6
Dependent Claim
38 words
A method according to Claim 4, characterised in that windows are formed in the passivating layer to expose respective underlying areas of the doped semiconductor layer in which contact material is deposited to form source and drain contacts.
Claim 7
Dependent Claim
30 words
A method according to Claim 5, characterised in that the compensating doping implant is performed following deposition of the source and drain contacts and using these contacts as a mask.
Claim 8
Independent Claim
28 words
A method according to any one of the preceding claims, characterised in that the intrinsic semiconductor layer and the doped semiconductor layer are deposited sequentially as separate layers.
Claim 9
Independent Claim
29 words
A method according to any one of Claims 1 to 6, characterised in that the doped semiconductor layer is formed by doping a thickness of the intrinsic semiconductor layer.
Claim 10
Dependent Claim
96 words
A thin film transistor comprising an intrinsic semiconductor layer which extends over, and is insulated from, a gate electrode on a substrate and which provides a channel region, doped semiconductor material overlying the intrinsic silicon layer and defining discrete source and drain contact regions adjacent respective ends of the channel region, characterised in that semiconductor material providing the source and drain contact regions extending as a layer also over the channel region with a portion thereof which separates the doped contact regions being resistive so as to inhibit conduction between the contact regions in that layer.
Claim 11
Dependent Claim
96 words
A thin film transistor comprising an intrinsic semiconductor layer which extends over, and is insulated from, a gate electrode on a substrate and which provides a channel region, doped semiconductor material overlying the intrinsic silicon layer and defining discrete source and drain contact regions adjacent respective ends of the channel region, characterised in that semiconductor material providing the source and drain contact regions extending as a layer also over the channel region with a portion thereof which separates the doped contact regions being resistive so as to inhibit conduction between the contact regions in that layer.
Claim 12
Dependent Claim
41 words
A thin film transistor according to Claim 9, characterised in that a passivating layer extends over the layer of semiconductor material which is provided with windows through which source and drain contacts extend onto the doped source and drain contact regions.
Claim 13
Dependent Claim
29 words
A thin film transistor according to Claim 9 or Claim 10, characterised in that the semiconductor of the intrinsic semiconductor layer and the semiconductor material layer comprises amorphous silicon.
Claim 14
Dependent Claim
28 words
A thin film transistor according to Claim 9 or Claim 10, characterised in that the semiconductor of the intrinsic semiconductor layer and the semiconductor material layer comprise polysilicon.
Claim 15
Dependent Claim
54 words
An electro-optical display device comprising an array of display elements each of which is controlled via a switching element, characterised in that the switching elements comprise thin film transistors in accordance with any one of Claims 9 to 12 or thin film transistors fabricated in accordance with any one of Claims 1 to 8.
Claim 16
Dependent Claim
19 words
An electro-optical display device according to Claim 13, characterised in that the display elements comprise liquid crystal display elements.
References Cited (Backward Citations)
No citation records indexed.
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