Method and apparatus for increasing image generation speed on raster displays

Claim 2

Apparatus for increasing the speed of displaying images on raster display means for displaying image data in the form of images, comprising: a graphics system processor for receiving information to be displayed, at least a portion of the information being in the form of X,Y coordinate data, the graphics system processor for transposing each received set of X and Y coordinates so that X,Y becomes Y,X and then for processing adjacent pairs of transposed coordinates to generate at least one line segment by using the first set of transposed coordinates as the starting point and the second set of transposed coordinates as the end point to generate image data and addresses for storage of the image data; a video memory connected to the graphics system processor for storing image data, the video memory being connected to the raster display means; and an address translator circuit connected between the graphics system processor and the video memory for enabling the writing of image data into the video memory so that the image data is properly fed under control of the graphics system processor to modulate the electron beam of the raster display means.

Claim 3

The apparatus of claim 1 wherein the address translator circuit writes into the video memory by reversing address select lines to the video memory so that the image data is correctly stored for later access.

Claim 4

The apparatus of claim 2 wherein the address translator circuit enables the image data to be written into the video memory in banks of vertically oriented image data, as compared to horizontally oriented banks of image data, so that the image data is stored in the video memory in a conventional format for updating images on the raster display means.

Claim 5

The apparatus of claim 1 wherein the raster display means is a CRT.

Claim 6

The apparatus of claim 1 wherein the graphics system processor computes a best-fit set of points between the starting and end points to interconnect them using Bresenham's line-drawing algorithm.

Claim 7

The apparatus of claim 1, further comprising a pulse stretching circuit connected between the video memory and the raster display means for replicating an adjacent pixel for each pixel of each line segment to provide a smooth, high resolution trace.

Claim 8

Apparatus for speeding generation of images on raster display means, comprising the steps of: a display list memory for storing raw data, at least a portion of the raw data being stored in the display list memory in X,Y coordinate form; a video memory; a graphics system processor connected to the display list memory and programmed for reading raw data from the display list memory on an I/0 data bus which interconnects the graphics system processor and the display list memory, the graphics system processor after reading the raw data in X,Y coordinate form for transposing the raw data to Y,X coordinate form and then commencing a line drawing operation which translates the raw data to a pictorial representation in the form of image data, the image data generated by the graphics system processor appearing on the I/O data bus in Y,X coordinate form with the Y,X coordinate address information appearing on first and second output address lines of the graphics system processor, such that a video memory address that is generated will have the least significant portion generated from the Y value and the most significant portion generated from the X value; and an address translator circuit for converting the address information on the first and second output address lines of the graphics system processor to X and Y coordinate information appearing on third and fourth address lines, respectively, to exchange the upper and lower portions of the address bus before presenting the address to the video memory so that the Y-half (low order bits now) determine the row address in the video memory and the X-half of the address (higher order bits now) determine the column address in the video memory; the video memory being connected to the third and fourth address lines and the data I/O bus for receiving image data, the video memory storing image data in memory locations identified by the address information on the third and fourth address lines to write the image data into the appropriate memory locations for generating images on the raster display means.

Claim 9

Apparatus for speeding generation of images on raster display means, comprising the steps of: a display list memory for storing raw data, at least a portion of the raw data being stored in the display list memory in X,Y coordinate form; a video memory; a graphics system processor connected to the display list memory and programmed for reading raw data from the display list memory on an I/0 data bus which interconnects the graphics system processor and the display list memory, the graphics system processor after reading the raw data in X,Y coordinate form for transposing the raw data to Y,X coordinate form and then commencing a line drawing operation which translates the raw data to a pictorial representation in the form of image data, the image data generated by the graphics system processor appearing on the I/O data bus in Y,X coordinate form with the Y,X coordinate address information appearing on first and second output address lines of the graphics system processor, such that a video memory address that is generated will have the least significant portion generated from the Y value and the most significant portion generated from the X value; and an address translator circuit for converting the address information on the first and second output address lines of the graphics system processor to X and Y coordinate information appearing on third and fourth address lines, respectively, to exchange the upper and lower portions of the address bus before presenting the address to the video memory so that the Y-half (low order bits now) determine the row address in the video memory and the X-half of the address (higher order bits now) determine the column address in the video memory; the video memory being connected to the third and fourth address lines and the data I/O bus for receiving image data, the video memory storing image data in memory locations identified by the address information on the third and fourth address lines to write the image data into the appropriate memory locations for generating images on the raster display means.

Claim 10

The apparatus of claim 7 wherein the video memory comprises 16 VRAMs arranged as four banks of four.

Claim 11

The apparatus of claim 8 wherein the video memory comprises conventional 256K-bit video memories arranged as 64K x 4 VRAMs.

Claim 12

The apparatus of claim 7 wherein the video memory comprises a video memory shift register into which image data for drawing each individual row of the raster display means is sequentially written and subsequently fed on a video data bus to the raster display means.

Claim 13

The apparatus of claim 10 wherein the raster display means is a CRT.

Claim 14

The apparatus of claim 11 wherein the CRT is a color monitor.

Claim 15

The apparatus of claim 7 wherein the graphics system processor executes a fill rectangle command for performing actual line drawing.

Claim 16

The apparatus of claim 10, further comprising a pixel processing circuit connected between the video memory shift register and the raster display means for replicating pixels based on the image data that appears on the video data bus to double the width of a trace displayed on the raster display means.

Claim 17

The apparatus of claim 14, further comprising a video palette connected between the pixel processing circuit and the raster display means for converting the image data to analog signals which are input to the raster display means.

Claim 20

exchanging X and Y halves of video memory addresses computed by the graphics system processor by means of an address translator circuit so that image data is written into a video memory in an appropriate format for generating a raster display.

Claim 21

exchanging X and Y halves of video memory addresses computed by the graphics system processor by means of an address translator circuit so that image data is written into a video memory in an appropriate format for generating a raster display.

Claim 22

The method of claim 16 wherein computing vertical line segments comprises the steps of: reading raw data in X,Y coordinate form by means of the graphics system processor; transposing the raw data to Y,X coordinate form by means of the graphics system processor; determining the horizontal separation between adjacent points of the transposed data by means of the graphics system processor; determining the vertical spacing by means of the graphics system processor if the horizontal spacing is less than a predetermined distance; breaking the line into a set of vertical line segments offset horizontally from one another by one pixel by means of the graphics system processor if the vertical spacing is greater than the horizontal separation, i.e., the slope is greater than 45 degrees; breaking the line into two segments of equal length, ignoring round-off, by means of the graphics system processor, if the cumulative offset between X coordinates is one; and if, on the other hand, the cumulative offset is two or more, computing the number of segments to be Delta X plus 1, where Delta X equals the number of pixels separating the adjacent X coordinates, determining the length of each vertical segment by computing the vertical spacing so as to determine the number of pixels between the Y coordinates of the adjacent points, inclusive of the end points, and dividing the result by Delta X, ignoring round-off, and, finally, setting the first and last segments to be half the length (number of pixels) of the remaining segments by means of the graphics system processor.

Claim 23

The method of claim 17, further comprising the step of pixel stretching so that if the current pixel is a background color, then the previous value of the pixel is output, and if the current pixel is not a background color, then the current pixel is output.

Claim 26

The method of claim 19, further comprising the steps of: drawing a line using a conventional "LINE" command to write one pixel at a time into the video memory, if the slope of the reversed line is not nearly horizontal; reversing the upper and lower halves of the address bus, essentially reversing X and Y values; and performing a read/modify/write process by reading a predetermined number of vertically adjacent pixels from the video memory, masking all but one, and modifying one, and then writing the resultant pixel data into the predetermined vertically adjacent memory cells in the video memory so that the pixel data is thus written into the video memory in conventional format.