Patent EP0403122A2 successfully refreshed from Google Patents.
EP0403122A2
Expired / Lapsed
EP
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Processor controlled image overlay
Assignee: International Business Machines Corp
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Filing: 1990-05-31
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Granted: —
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Expires: 2010-05-31
Abstract
Abstract A data processing system is described which includes, among others, three memory areas: a source memory which is addressed in planar, data unit increments and stores display data units on a bit per plane basis; a target memory for storing display data units in a manner suitable for operation of a display unit; and a window buffer for transferring display data units from the source memory to the target memory. The system includes apparatus for inhibiting certain data units from the source memory from overwriting data units already in the target memory. The method of the invention comprises first accessing a plurality of data units from the source memory and then logically determining if all bits of each accessed data unit meet a predetermined criteria. Each data unit found to meet the predetermined criteria is inhibited from altering any data unit already in the target memory.
Inventors
- 👤 Michael William Ronald Bayley
- 👤 Peter Cornelius Yanker
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-05 13:35
CPC Classifications
G; G09; G09G; G09G5/00; G09G5/36; G09G5/39; G09G5/393
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
69 words
A display system having a display memory and a source memory, relatively non-aligned, a window register mechanism for aligning data accessed from the source memory before transmission to the "target" display memory and activity detection means responsive to the loading of the window register mechanism with overlay data to detect inactive overlay display positions and isolating the corresponding locations in the display memory from the subsequent overlay writing operation.
Claim 2
Dependent Claim
69 words
A display system having a display memory and a source memory, relatively non-aligned, a window register mechanism for aligning data accessed from the source memory before transmission to the "target" display memory and activity detection means responsive to the loading of the window register mechanism with overlay data to detect inactive overlay display positions and isolating the corresponding locations in the display memory from the subsequent overlay writing operation.
Claim 3
Dependent Claim
36 words
A system as claimed in claim 1, wherein the source memory is organised in a bit-planar manner and the activity detection means detects for a null contribution from each bit-plane contributing to a display overlay position.
Claim 4
Dependent Claim
136 words
In a data processing system including a bit planar oriented data unit source memory; a target memory having a plurality of planes, each plane comprising a plurality of data units including serially arranged multi-bit data units; buffer for transferring data from said source memory to said target memory; and transfer inhibit means for preventing certain data units from overwriting data units already in said target memory, the transfer inhibit method comprising: (a) accessing and aligning a plurality of data units from said source memory (b) determining logically if all bits of each accessed data unit meet a predetermined criteria; (c) passing a discrete number of aligned data units through said buffer means; (d) inhibiting alteration of any data unit in said target memory by any data unit from said buffer means which meets said predetermined criteria.
Claim 5
Dependent Claim
136 words
In a data processing system including a bit planar oriented data unit source memory; a target memory having a plurality of planes, each plane comprising a plurality of data units including serially arranged multi-bit data units; buffer for transferring data from said source memory to said target memory; and transfer inhibit means for preventing certain data units from overwriting data units already in said target memory, the transfer inhibit method comprising: (a) accessing and aligning a plurality of data units from said source memory (b) determining logically if all bits of each accessed data unit meet a predetermined criteria; (c) passing a discrete number of aligned data units through said buffer means; (d) inhibiting alteration of any data unit in said target memory by any data unit from said buffer means which meets said predetermined criteria.
Claim 6
Dependent Claim
39 words
A method as claimed in claim 3, wherein said source memory data unit is a Pel and comprises a plurality of bits, one bit per plane and said target memory is a Pel oriented memory for controlling a display.
Claim 7
Dependent Claim
40 words
A method as claimed in claim 4, wherein said determining step comprises: (e) Or'ing all data bits of each Pel together to determine if each said Pel is non-zero or zero, said predetermined criteria being a Pel equal to zero.
Claim 8
Dependent Claim
91 words
A method as claimed in claim 5, wherein said transfer inhibit means is a bit mask having a position corresponding to each of a plurality of Pels, the inhibiting step further comprising: (f) inserting in each corresponding mask position, an "inhibit write" indication for each Pel whose Or condition, as determined in step (e), is zero; and (g) passing the bits of each Pel from said buffer means under control of the corresponding mask position, whereby bits from any zero Pel do not overwrite corresponding bit positions in said target memory.
Claim 9
Dependent Claim
79 words
A method as claimed in claim 6, wherein said source memory comprises a plurality of planes, each plane including one bit of a multi-bit Pel code, each plane addressable on a two byte basis, the method further comprising, after said accessing step (a): (h) aligning a plural Pel segment of said two bytes to a preset boundary (i) inserting said aligned, plural Pel segments into a window buffer, one side of said window buffer coincident with said preset boundary
Claim 10
Dependent Claim
32 words
A method as claimed in claim 7, wherein said bit mask: (j) inhibits the transfer of any Pel bits from said window buffer when the OR value of said Pel equals zero
Claim 11
Dependent Claim
103 words
In a data processing system for transferring Pel bits of display data from a bit-planar, byte organised source memory through an N byte window buffer, to a display memory, the combination comprising: (a) register means for aligning N Pels from said source memory; (b) bit mask means having a position corresponding to each Pel in said window buffer; (c) logic means for ORing all bits in each Pel to determine non-zero Pels, and setting said bit mask means to pass such Pels; and (d) means controlled by said bit-mask means for writing only non-zero Pels from said window buffer into said target memory.
Claim 12
Dependent Claim
103 words
In a data processing system for transferring Pel bits of display data from a bit-planar, byte organised source memory through an N byte window buffer, to a display memory, the combination comprising: (a) register means for aligning N Pels from said source memory; (b) bit mask means having a position corresponding to each Pel in said window buffer; (c) logic means for ORing all bits in each Pel to determine non-zero Pels, and setting said bit mask means to pass such Pels; and (d) means controlled by said bit-mask means for writing only non-zero Pels from said window buffer into said target memory.
References Cited (Backward Citations)
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