Patent EP0408129A2 successfully refreshed from Google Patents.
EP0408129A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
A thin film field effect transistor
Assignee: Philips Electronics UK Ltd
•
Filing: 1990-07-06
•
Granted: —
•
Expires: 2010-07-06
Abstract
Abstract A thin film field effect transistor (1) is formed by an insulating substrate (2,3) carrying a semiconductor layer (4) having a polycrystalline channel region (5) which is passivated to reduce the density of charge carrier traps. Source and drain electrodes (6 and 7) contact opposite ends (5a,5b) of the channel region (5), and a gate electrode (8) is provided at one major surface (4a) of the semiconductor layer (4) for controlling a conduction channel of one conductivity type in the polycrystalline channel region (5) to provide a gateable connection between the source and drain electrodes (6 and 7). An area (50) of the polycrystalline channel region (5) spaced from the electrodes (6,7,8) of the transistor (1) and lying adjacent to the other major surface (4b) of the semiconductor layer (4) is doped with impurities of the opposite conductivity type for suppressing formation of a conduction channel of the one conductivity type adjacent to the other major surface (4b).
Inventors
- 👤 Stanley David Brotherton
- 👤 John Richard Alan Ayres
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-30 13:20
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/67; H10D30/6704; H10D30/6706; H10D30/01; H10D30/021; H10D30/031; H10D30/0312; H10D30/0314; H10D30/6729; H10D30/673; H10D30/6731; H10D30/6757
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
135 words
A thin film field effect transistor, comprising an insulating substrate carrying a semiconductor layer having a polycrystalline channel region which is passivated to reduce the density of charge carrier traps, source and drain electrodes contacting opposite ends of the channel region, and a gate electrode provided at one major surface of the semiconductor layer for controlling a conduction channel of one conductivity type in the polycrystalline channel region to provide a gateable connection between the source and drain regions, characterised in that an area of the polycrystalline channel region spaced from the electrodes of the transistor and lying adjacent to the other major surface of the semiconductor layer is doped with impurities of the opposite conductivity type for supressing formation of a conduction channel of the one conductivity type adjacent to the other major surface.
Claim 2
Dependent Claim
135 words
A thin film field effect transistor, comprising an insulating substrate carrying a semiconductor layer having a polycrystalline channel region which is passivated to reduce the density of charge carrier traps, source and drain electrodes contacting opposite ends of the channel region, and a gate electrode provided at one major surface of the semiconductor layer for controlling a conduction channel of one conductivity type in the polycrystalline channel region to provide a gateable connection between the source and drain regions, characterised in that an area of the polycrystalline channel region spaced from the electrodes of the transistor and lying adjacent to the other major surface of the semiconductor layer is doped with impurities of the opposite conductivity type for supressing formation of a conduction channel of the one conductivity type adjacent to the other major surface.
Claim 3
Dependent Claim
21 words
A transistor according to Claim 1, wherein the semiconductor layer comprises polycrystalline silicon and the channel region is passivated with hydrogen.
Claim 4
Dependent Claim
27 words
A transistor according to Claim 1 or 2, wherein the gate electrode comprises a conductive polycrystalline silicon region insulated from the one surface of the semiconductor layer.
Claim 5
Dependent Claim
46 words
A transistor according to Claim 1, 2 or 3, wherein the semiconductor layer is provided at each end of the channel region with a highly doped region of the one conductivity type forming an ohmic contact with a respective one of the source and drain electrodes.
Claim 6
Dependent Claim
21 words
A transistor according to Claim 4, wherein the opposite conductivity type doped area forms pn junctions with the highly doped regions.
Claim 7
Dependent Claim
35 words
A transistor according to any one of the preceding claims, wherein the source, gate and drain electrodes are provided at the one major surface and the other major surface is adjacent to the insulating substrate.
Claim 8
Independent Claim
145 words
A method of manufacturing a thin film field effect transistor, which method comprises depositing a semiconductor layer for forming a polycrystalline channel region on an insulating substrate, providing source and drain electrodes contacting opposite ends of the channel region, defining a gate electrode at one major surface of the semiconductor body for controlling a conduction channel of the one conductivity type in the polycrystalline channel region to provide a gateable connection between the source and drain electrodes and passivating the channel region so as to reduce the density of charge carrier traps, characterised by doping an area of the polycrystalline channel region spaced from the electrodes of the transistor and lying adjacent to the other major surface of the semiconductor body with impurities of the opposite conductivity type for suppressing formation of a conduction channel of the one conductivity type adjacent the other major surface.
Claim 9
Independent Claim
145 words
A method of manufacturing a thin film field effect transistor, which method comprises depositing a semiconductor layer for forming a polycrystalline channel region on an insulating substrate, providing source and drain electrodes contacting opposite ends of the channel region, defining a gate electrode at one major surface of the semiconductor body for controlling a conduction channel of the one conductivity type in the polycrystalline channel region to provide a gateable connection between the source and drain electrodes and passivating the channel region so as to reduce the density of charge carrier traps, characterised by doping an area of the polycrystalline channel region spaced from the electrodes of the transistor and lying adjacent to the other major surface of the semiconductor body with impurities of the opposite conductivity type for suppressing formation of a conduction channel of the one conductivity type adjacent the other major surface.
Claim 10
Dependent Claim
26 words
A method according to Claim 7, which comprises depositing the semiconductor layer to form a layer of polycrystalline silicon and passivating the channel region with hydrogen.
Claim 11
Dependent Claim
29 words
A method according to Claim 7 or 8, which comprises defining the gate electrode as a conductive polycrysatlline silicon region insulated from the one surface of the semiconductor layer.
Claim 12
Dependent Claim
43 words
A method according to Claim 7, 8 or 9, which comprises doping each end of the channel region to form highly doped regions of the one conductivity type each providing an ohmic contact with a respective one of the source and drain electrodes.
Claim 13
Dependent Claim
48 words
A method according to Claim 10, which comprises implanting impurities of the opposite conductivity type to form the doped area prior to defining the highly doped regions so that, after formation of the highly doped regions, the doped area forms a pn junction with each highly doped region.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.