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EP0411573A2
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Nonvolatile semiconductor memory device and method of operating the same
Assignee: Toshiba Corp
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Filing: 1990-07-31
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Granted: —
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Expires: 2010-07-31
Abstract
Abstract In a nonvolatile semiconductor memory device such as EEPROMs which comprises a semiconductor substrate (101) of one conductivity type having source (103) and drain (102) regions of opposite conductivity type for defining a channel region (104) therebetween, and a stacked gate including a gate insulating film (105), a floating gate (106) and a control gate (108) provided through an interlevel insulator (107) above the floating gate (106), an erase gate (111) having an electrode (115) is provided above the channel region (104) through an insulating film (110) which is contiguous to the gate insulating film (105). The erase gate is also insulated from the stacked gate through a side wall insulating film (109). For removing a charge carrier stored in the floating gate (106), a high voltage is applied to the erase gate (111), while grounding the source (103) and drain (102) regions and the control gate (108), respectively.
Inventors
- 👤 Kiyomi C/O Intellectual Property Division Naruke
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-29 09:31
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0411; G; G11; G11C; G11C16/00; G11C16/02; G11C16/04; G11C16/0408; G11C16/0416; H10D30/60; H10D30/68; H10D30/681; H10D30/684; H10D30/685
Claims Analysis
Total Claims: 21
Claim 1
Independent Claim
137 words
A nonvolatile semiconductor memory device comprising a semiconductor substrate (101) of one conductivity type having source and drain regions (103, 102) of opposite conductivity type for defining a channel region (104) therebetween, and a stacked gate which is provided on said channel region (104) and includes a gate insulating film (105) overlapping said drain region (102), a floating gate (106) disposed on said gate insulating film (105) and a control gate (108) provided through an interlevel insulator (107) above said floating gate (106), characterized in that an erase gate (111) with an electrode is provided above said channel region (104) through an insulating film (110) which is contiguous to said gate insulating film (105) and overlaps said source region (103), said erase gate (111) being insulated from said stacked gate through a side wall insulating film (109).
Claim 2
Dependent Claim
137 words
A nonvolatile semiconductor memory device comprising a semiconductor substrate (101) of one conductivity type having source and drain regions (103, 102) of opposite conductivity type for defining a channel region (104) therebetween, and a stacked gate which is provided on said channel region (104) and includes a gate insulating film (105) overlapping said drain region (102), a floating gate (106) disposed on said gate insulating film (105) and a control gate (108) provided through an interlevel insulator (107) above said floating gate (106), characterized in that an erase gate (111) with an electrode is provided above said channel region (104) through an insulating film (110) which is contiguous to said gate insulating film (105) and overlaps said source region (103), said erase gate (111) being insulated from said stacked gate through a side wall insulating film (109).
Claim 3
Dependent Claim
27 words
A nonvolatile semiconductor memory device according to claim 1, characterized in that a thickness of said gate insulating film (105) is of the order of 100 Å.
Claim 4
Dependent Claim
28 words
A nonvolatile semiconductor memory device according to claim 1, characterized in that a thickness of said side wall insulating film (109) is of the order of 800 Å.
Claim 5
Dependent Claim
28 words
A nonvolatile semiconductor memory device according to claim 1, characterized in that a comparatively low impurity concentration region of opposite conductivity type is provided underneath said drain region.
Claim 6
Dependent Claim
21 words
A nonvolatile semiconductor memory device according to claim 1, characterized in that said channel region (104) has a controlled threshold voltage.
Claim 7
Dependent Claim
32 words
A nonvolatile semiconductor memory device according to claim 1, characterized in that said interlevel insulator (107) is comprised of a silicon oxide film, a silicon nitride film and a silicon oxide film.
Claim 8
Independent Claim
196 words
A method of erasing stored information from a nonvolatile semiconductor memory device which comprises a semiconductor substrate (101) of one conductivity type having source and drain regions (103, 102) of opposite conductivity type for defining a channel region (104) therebetween, and a stacked gate which is provided on said channel region (104) and includes a gate insulating film (105) overlapping said drain region (102), a floating gate (106) disposed on said gate insulating film (105) and control gate (108) provided through an interlevel insulator (107) above said floating gate (106), characterized in that an erase gate (111) with an electrode is provided above said channel region (104) through an insulating film (110) which is contiguous to said gate insulating film (105) overlaps said source region (103), said erase gate (111) being insulated from said stacked gate through a side wall insulating film (109), and that applying a high voltage to said erase gate (111) through said erase electrode while grounding said source and drain regions (103, 102) and said control gate (108), respectively, thereby removing a charge carrier, stored in said floating gate (106), toward said erase gate (111) through said side wall insulating film (109).
Claim 9
Independent Claim
196 words
A method of erasing stored information from a nonvolatile semiconductor memory device which comprises a semiconductor substrate (101) of one conductivity type having source and drain regions (103, 102) of opposite conductivity type for defining a channel region (104) therebetween, and a stacked gate which is provided on said channel region (104) and includes a gate insulating film (105) overlapping said drain region (102), a floating gate (106) disposed on said gate insulating film (105) and control gate (108) provided through an interlevel insulator (107) above said floating gate (106), characterized in that an erase gate (111) with an electrode is provided above said channel region (104) through an insulating film (110) which is contiguous to said gate insulating film (105) overlaps said source region (103), said erase gate (111) being insulated from said stacked gate through a side wall insulating film (109), and that applying a high voltage to said erase gate (111) through said erase electrode while grounding said source and drain regions (103, 102) and said control gate (108), respectively, thereby removing a charge carrier, stored in said floating gate (106), toward said erase gate (111) through said side wall insulating film (109).
Claim 10
Dependent Claim
31 words
A method of erasing stored information from a nonvolatile semiconductor memory device according to claim 7, characterized in that a voltage of +20 volts is applied to said erase gate (111).
Claim 11
Dependent Claim
29 words
A method of erasing stored information from a nonvolatile semiconductor memory device according to claim 8, characterized in that said high voltage is provided by on-chip charge pumping circuitry.
Claim 12
Dependent Claim
181 words
A nonvolatile semiconductor memory device comprising a semiconductor substrate (101) of one conductivity type having source and drain regions (103, 102) of opposite conductivity type for defining a channel region (104) therebetween, a stacked gate which is provided on said channel region (104) and includes a gate insulating film (105) overlapping said drain region (102), a floating gate (106) disposed on said gate insulating film (105) and a control gate (108) provided through an interlevel insulator (107) above said floating gate (106), and a select gate (111a) provided above said channel region (104) through an insulating film (110a) which is contiguous to said gate insulating film (105) and overlaps said source region (103), said select gate (111a) being insulated from said stacked gate through one side wall insulating film (109a), characterized in that an erase gate (111b) with an electrode is provided on an insulating film (110b) which is contiguous to said gate insulating film (105) and extends to said drain region (102), said erase gate (111b) being insulated from said stacked gate through the other side wall insulating film (109b).
Claim 13
Dependent Claim
181 words
A nonvolatile semiconductor memory device comprising a semiconductor substrate (101) of one conductivity type having source and drain regions (103, 102) of opposite conductivity type for defining a channel region (104) therebetween, a stacked gate which is provided on said channel region (104) and includes a gate insulating film (105) overlapping said drain region (102), a floating gate (106) disposed on said gate insulating film (105) and a control gate (108) provided through an interlevel insulator (107) above said floating gate (106), and a select gate (111a) provided above said channel region (104) through an insulating film (110a) which is contiguous to said gate insulating film (105) and overlaps said source region (103), said select gate (111a) being insulated from said stacked gate through one side wall insulating film (109a), characterized in that an erase gate (111b) with an electrode is provided on an insulating film (110b) which is contiguous to said gate insulating film (105) and extends to said drain region (102), said erase gate (111b) being insulated from said stacked gate through the other side wall insulating film (109b).
Claim 14
Dependent Claim
27 words
A nonvolatile semiconductor memory device according to claim 10, characterized in that a thickness of said gate insulating film (105) is of the order of 100 Å.
Claim 15
Dependent Claim
29 words
A nonvolatile semiconductor memory device according to claim 10, characterized in that a thickness of each of said side wall insulating film is of the order of 800 Å.
Claim 16
Dependent Claim
21 words
A nonvolatile semiconductor memory device according to claim 10, characterized in that said channel region (104) has a controlled threshold voltage.
Claim 17
Dependent Claim
31 words
A nonvolatile semiconductor memory device according to claim 10, characterized in that said interlevel insulator (107) is comprised of a silicon oxide film, silicon nitride film and a silicon oxide film.
Claim 18
Independent Claim
251 words
A method of erasing stored information from a nonvolatile semiconductor memory device which comprises a semiconductor substrate (101) of one conductivity type having source and drain regions (103, 102) of opposite conductivity type for defining a channel region (104) therebetween, a stacked gate which is provided on said channel region (104) and includes a gate insulating film (105) overlapping said drain region (102), a floating gate (106) disposed on said gate insulating film (105) and a control gate (108) provided through an interlevel insulator (107) above said floating gate (106), and a select gate (111a) provided above said channel region (104) through an insulating film (110a) which is contiguous to said gate insulating film (105) and overlaps said source region (103), said select gate (111a) being insulated from said stacked gate through one side wall insulating film (109a), characterized in that an erase gate (111b) with an electrode is provided above said channel region (104) through an insulating film (110b) which is contiguous to said gate insulating film (105) and extends to said drain region (102), said erase gate (111b) being insulated from said stacked gate through the other side wall insulating film (109b), and that applying a high voltage to said erase gate (111b) through said erase electrode while grounding said source and drain regions (103, 102), said control gate (108) and said select gate (111a), respectively, thereby removing a charge carrier, stored in said floating gate (106), toward said erase gate (111b) through said side wall insulating film (109b).
Claim 19
Independent Claim
251 words
A method of erasing stored information from a nonvolatile semiconductor memory device which comprises a semiconductor substrate (101) of one conductivity type having source and drain regions (103, 102) of opposite conductivity type for defining a channel region (104) therebetween, a stacked gate which is provided on said channel region (104) and includes a gate insulating film (105) overlapping said drain region (102), a floating gate (106) disposed on said gate insulating film (105) and a control gate (108) provided through an interlevel insulator (107) above said floating gate (106), and a select gate (111a) provided above said channel region (104) through an insulating film (110a) which is contiguous to said gate insulating film (105) and overlaps said source region (103), said select gate (111a) being insulated from said stacked gate through one side wall insulating film (109a), characterized in that an erase gate (111b) with an electrode is provided above said channel region (104) through an insulating film (110b) which is contiguous to said gate insulating film (105) and extends to said drain region (102), said erase gate (111b) being insulated from said stacked gate through the other side wall insulating film (109b), and that applying a high voltage to said erase gate (111b) through said erase electrode while grounding said source and drain regions (103, 102), said control gate (108) and said select gate (111a), respectively, thereby removing a charge carrier, stored in said floating gate (106), toward said erase gate (111b) through said side wall insulating film (109b).
Claim 20
Dependent Claim
30 words
A method of erasing stored information from a nonvolatile semiconductor memory device according to claim 15, characterized in that a voltage of +20 volts is applied to said erase gate.
Claim 21
Dependent Claim
29 words
A method of erasing stored information from a nonvolatile semiconductor memory device according to claim 16, characterized in that said high voltage is provided by on-chip charge pumping circuitry.
References Cited (Backward Citations)
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