Patent EP0427407A2 successfully refreshed from Google Patents.
EP0427407A2
Expired / Lapsed
EP
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Parallel port with direct memory access capabilities
Assignee: Compaq Computer Corp
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Filing: 1990-10-16
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Granted: —
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Expires: 2010-10-16
Abstract
Abstract The parallel or printer port (112) in a personal computer can receive data from the memory under the control of the direct memory access (DMA) controller (56), releasing processor resources. The processor (20) enables the parallel port, which then indicates to the DMA controller the desire to transfer data. A state machine in the parallel port, along with associated circuitry, responds to the transfer of the data to the parallel port and then controls the transfer of the data to the attached device, usually a printer (114). The state machine causes an interrupt to the processor (20) when the transfer is complete or an receipt of errors from the external device. The state machine also communicates with the DMA controller to repeat the transfer process until the transfer is complete or an error occurs. Various DMA channels and parallel port locations can be used. Direct transfers by the processor are blocked during DMA controller handled transfers.
Inventors
- 👤 James J. Jirgal
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-01 18:35
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/38; G06F13/42; G06F13/4265; G06F13/4269; G06F13/14; G06F13/20; G06F13/28; G06F2213/00; G06F2213/0004
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
104 words
A computer system for communicating with an external device (114) in a parallel format, comprising: a microprocessor (20); memory means (58) coupled to said microprocessor for storing instructions and data for said microprocessor and data to be communicated to the external device; a direct memory access controller (56) coupled to said memory means for controlling the transfer of data from said memory means; and parallel output port means (112) coupled to said memory means and said direct memory access controller for receiving data from said memory means under control of said direct memory access controller and for providing said data to the external device.
Claim 2
Dependent Claim
104 words
A computer system for communicating with an external device (114) in a parallel format, comprising: a microprocessor (20); memory means (58) coupled to said microprocessor for storing instructions and data for said microprocessor and data to be communicated to the external device; a direct memory access controller (56) coupled to said memory means for controlling the transfer of data from said memory means; and parallel output port means (112) coupled to said memory means and said direct memory access controller for receiving data from said memory means under control of said direct memory access controller and for providing said data to the external device.
Claim 3
Dependent Claim
31 words
The computer system of claim 1, wherein said parallel output port means includes means (130) for developing a signal for use by the external device to indicate that data is available.
Claim 4
Dependent Claim
33 words
The computer system of claim 1 or claim 2, wherein said parallel output port means includes means (130) for receiving a signal from the external device indicating that the data has been accepted.
Claim 5
Dependent Claim
33 words
The computer system of claim 1, claim 2 or claim 3, wherein said parallel output port means includes means (130) for receiving a signal from the external device that an error has occurred.
Claim 6
Dependent Claim
39 words
The computer system of claim 3, wherein said parallel output port means includes means (128) for indicating to said direct memory access controller to initiate the transfer of data from said memory means to said parallel output port means.
Claim 7
Dependent Claim
61 words
The computer system of any of claims 1 to 5, wherein said direct memory access controller indicates to said parallel output port means that the data transfer has been completed and where said parallel output port means is coupled to said microprocessor, said parallel output port means including means (200) for indicating to said microprocessor that said data transfer is completed.
Claim 8
Dependent Claim
21 words
The computer system of claim 6, wherein said parallel output port means data transfer complete means (200) interrupts said microprocessor operation.
Claim 9
Dependent Claim
51 words
The computer system of any of claims 1 to 7, wherein said parallel output port means is coupled to said microprocessor by means other than said direct memory access controller and wherein said parallel output port means includes means for receiving data from said microprocessor for providing to the external device.
Claim 10
Dependent Claim
36 words
The computer system of claim 8, wherein parallel output port means for receiving data from said microprocessor is disabled when said parallel output port means is receiving data under control of said direct memory access controller.
Claim 11
Dependent Claim
52 words
The computer system of any of claims 1 to 9, wherein said parallel output port means is coupled to said microprocessor and said parallel output port means includes means (300) controllable by said microprocessor to initiate said parallel output port means receiving data under the control of said direct memory access means.
Claim 12
Dependent Claim
49 words
The computer system of any of claims 1 to 10, wherein said direct memory access controller includes a plurality of channels and said parallel output port means includes means (320) for selecting the channel of said direct memory access controller to be used by said parallel output port means.
Claim 13
Dependent Claim
24 words
The computer system of any of claims 1 to 11, wherein said parallel output port means can reside at a plurality of address locations.
References Cited (Backward Citations)
No citation records indexed.
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