Patent EP0437515B1 successfully refreshed from Google Patents.
EP0437515B1
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EP
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Integrated telecommunication system with improved digital voice response
Assignee: Precision Software Inc
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Filing: 1989-10-03
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Granted: 1998-01-14
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Expires: 2009-10-03
Abstract
No abstract record available.
Inventors
- 👤 Ferrell W. Boyd, Jr.
- 👤 Michael Murdock
- 👤 Michael Mccormack
- 👤 Paul Darbee
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-29 07:19
CPC Classifications
H; H04; H04Q; H04Q11/00; H04Q11/04; H04Q11/0407; H04M; H04M3/00; H04M3/42; H04M3/50
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
318 words
An integrated telecommunication system for multiple telephone line
response and processing, comprising a main system control microprocessor
(60), a plurality of interface processor circuits (10) and a
bus system (10, 12); characterized in that each said plurality of interface processor circuits (10)
is adapted to control the physical connection to a plurality of telephone
lines channels (T1) and to control communication on a group
of said telephone line channels connected thereto, each said interface
circuit (10) including a high speed interface control microprocessor
(50) and a first data storage (56) associated therewith, in that said integrated telecommunication systems further comprises a plurality of signal processor circuit means (13), each said
signal processor circuit means (13) including crosspoint switch means
(65) for receiving multiple line multiple channel inputs and producing
corresponding multiple line multiple channel outputs, and a high
speed digital signal microprocessor (63) for analyzing incoming
signals and compressing data therein, and a second data storage (68)
associated therewith, for controlling one or more telecommunication
function circuits thereby; and in that said bus system (10, 12) comprises a first bus system (12) for connecting said plurality of interface
processor circuits (10) to said plurality of signal processor circuit
means (13), and a second bus system (11) for connecting each of said plurality
of interface processor circuits (10) to each of said plurality of
signal processor circuit means (13) and to said main system
control microprocessor (60), whereby said interface processor circuits (10) include means for
processing high speed processing requirements of each said group of
telephone lines and whereby said digital signal microprocessor (63)
and said main system control microprocessor (60) includes means for
controlling the storage of data in said first and second data storages
(56, 68) and intercommunication functions between said plurality of
interface processor circuits (10) and said plurality of signal processor
circuit means (13) and said one or more telecommunication function
circuits controlled thereby.
Claim 2
Dependent Claim
82 words
The integrated telecommunication system defined in claim 1 wherein
each of said plurality of interface processor circuits (10) includes a
telephone line interface circuit chip (51), call progress interface chip
(52) and a facility data link chip (55) and means connecting said
interface circuit chip (51), said call progress interface chip (52) and
said facility data link chip (55) to said high speed interface control
microprocessor (50), and means to supply a program (54) to said
high speed interface control microprocessor (50).
Claim 3
Dependent Claim
31 words
The integrated telecommunication system defined in claim 1, including
a permanent data storage means (76) and means connecting
said permanent data storage means (76) to said main system control
microprocessor (60).
Claim 4
Dependent Claim
310 words
An integrated telecommunication system for multiple telephone line
response and processing, comprising a main system control microprocessor
(60), a plurality of interface processor circuits (10) and a
bus system (10, 12); characterized in that each said plurality of interface processor circuits (10) is
adapted to control the physical connection to a plurality of telephone
line channels (T1), and control communication on a group of
said telephone line channels connected thereto, and each interface
processor circuit (10) including a high speed interface control microprocessor
(50), respectively, and in that said integrated telecommunication system further comprises a plurality of signal processor circuit means (13), each said signal
processor circuit means (13) including crosspoint switch means (65)
for receiving multiple line multiple channel inputs and producing
corresponding multiple line multiple channel outputs and a high
speed digital signal microprocessor (63) for analyzing the incoming
signals and compressing the data therein, and a second data storage
(68) associated therewith, for controlling one or more telecommunication
function circuits thereby; data storage means (74) connected to said main system control
microprocessor (60), said bus system (10, 12) comprising a first bus system (12) for connecting said plurality of interface
processor circuit means (13), and a second bus system (11) for connecting each of said plurality of
interface processor circuits (10) to each of said plurality of signal
processor circuit means (13) and to said main system control microprocessor
(60), whereby said interface processor circuits (10) include means for
processing high speed processing requirements of said group of
telephone line channels and whereby said digital signal microprocessor
(63) and said main system control microprocessor (60) include
means for controlling the storage of data in said data storage means
(74) and intercommunication functions between said plurality of
interface processor circuits (10) and said plurality of signal processor
circuit means (13) and said telecommunication function circuit means
controlled thereby.
Claim 5
Dependent Claim
62 words
The integrated telecommunication system defined in claim 4 wherein
each of said plurality of interface processor circuits (10) includes a
telephone line interface circuit chip (51), a call progress interface
chip (52) and a facility data link chip (55) to said high speed
interface control microprocessor (50), and means to supply a program
(54) to said high speed interface control microprocessor (50).
References Cited (Backward Citations)
No citation records indexed.
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