Patent EP0439693A2 successfully refreshed from Google Patents.
EP0439693A2
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Multiprocessing packet switching connection system having provision for error correction and recovery
Assignee: International Business Machines Corp
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Filing: 1990-10-31
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Granted: —
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Expires: 2010-10-31
Abstract
Abstract A large number of processing elements (604) (e.g. 4096) are interconnected by means of a high bandwidth switch (606). Each processing element (604) includes one or more general purpose microprocessors (1202), a local memory (1210) and a DMA controller (1206) that sends and receives messages through the switch (606) without requiring processor intervention. The switch (606) that connects the processing elements is hierarchical and comprises a network of clusters. Sixtyfour processing elements (604) can be combined to form a cluster and and sixtyfour clusters can be linked by way of a Banyan network. Messages are routed through the switch (606) in the form of packets which include a command field, a sequence number, a destination address, a source address, a data field (which can include subcommands), and an error correction code. Error correction is performed at the processing elements. If a packet is routed to a non-present or non-functional processor, the switch (606) reverses the source and destination field and returns the packet to the sender with an error flag. If the packet is misrouted to a functional processing element (604), the processing element (604) corrects the error and retransmits the packet through the switch (606) over a different path. In one embodiment, each processing element can be provided with a hardware accelerator for database functions. In this embodiment, the multiprocessor of the present invention can be employed as a coprocessor to a 370 host and used to perform database functions.
Inventors
- 👤 Richard Irwin Baum
- 👤 Charles H. Brotman
- 👤 James Walter Rymarczyk
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-02 16:12
CPC Classifications
G; G06; G06F; G06F15/00; G06F15/16; G06F15/163; G06F15/173; G06F15/17356; G06F15/17368; G06F15/17393; G06F11/00; G06F11/07; G06F11/0703; G06F11/0706; G06F11/0712; G06F11/0721; G06F11/0724; G06F11/0793; G06F11/14; G06F11/1402; G06F11/1415; G06F11/1443; G06F11/08; G06F11/10; G06F11/142; G06F11/1423
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
89 words
A multiprocessing system having at least three nodes, comprising: a first node (604) comprising means to transmit data comprising destination identifying information; a second node (604) coupled to said first node (604), said second node comprising means for receiving said data along a first path, means (1206) for detecting and correcting an error in said destination identifying information so as to form corrected destination identifying information and means for rerouting said data, along a second independent path, to a third node (604) identified by said corrected destination identifying information.
Claim 2
Dependent Claim
41 words
The multiprocessing system of claim 1 wherein said first, second and third nodes are processors and wherein said processors are each coupled to a self routing switch (606) by way of independent input (608, 612) and output (610, 614) data paths.
Claim 3
Dependent Claim
29 words
The multiprocessing system of claim 2 wherein said data is packetized and comprises a destination field including said destination identifying information and a source field identifying a source processor.
Claim 4
Dependent Claim
38 words
The multiprocessing system of claim 2 wherein said switch (606) comprises means for detecting when said destination field identifies a non-present processor, for reversing said source and destination fields and for rerouting said data to said source processor.
Claim 5
Independent Claim
191 words
A method of error recovery in a multiprocessor system connected by a switching network, wherein a first processor (604) in said system transmits a data packet having an address field comprising an address of a second processor (604) in said system, comprising the steps of: transmitting said packet from said first (604) processor to said switching network (606) by way of a first path; decoding said address field in said transmitted packet at said switching network (606); routing said packet by way of a first path from said switching network (606) to a third processor (604) in said system designated by said decoding; detecting at said third processor (604), an error in said address field of said packet; correcting said error at said third processor (604) to form a corrected address in said address field; retransmitting said packet having said corrected address from said third processor (604) to said switching network (606) by way of a second path; decoding said address field in said retransmitted packet at said switching network (606); and routing said retransmitted packet from said switching network to said second processor (604) by way of a third path.
Claim 6
Dependent Claim
67 words
The method of claim 5 comprising the further steps of: determining at said switch (606) if a decoded address corresponds to a non-operable processor; and when said determining determines that said decoded address corresponds to said non-operable processor, causing said switch (606) to exchange said source and destination fields in said packet and returning said packet to said first processor (604) by way of a fourth path;
Claim 7
Dependent Claim
286 words
A cluster controller (602) for use in a multiprocessor system comprising a plurality of processor clusters coupled by way of a switching network, said cluster controller (602) comprising: switching means (1002), connected to receive packets from said switching network, for distributing said packets from said switching network in accordance with a destination address; global storage means (1004) for storing data, said global storage means being connected to receive said packets from said switching means (1002); queue means (1008) for buffering packet flow to a plurality of processors, said queue means comprising a plurality of packet queues associated with each of said processors; a plurality of first busses, each of said first busses being connected to an output port of said switching means and an input port of one of said packet queues, said first busses having a first number of bits; a plurality of processing element port means (612, 614) for transferring data between said cluster controller and said processors; a plurality of second busses, each of said second busses being connected to an output port of one of said packet queues and an input port (612) of one of said processing element port means, assembly buffer means (1006) for assembling data from said processors into packets, said assembly buffer means (1006) comprising one assembly buffer (1014) for each of said processors and round robin means for selecting an assembled packet to be output, said assembly buffer means (1006) being connected to receive said data from said processing element ports; and selector means (1016) for selecting one packet to be sent to said switching network (606), said selector means being connected to receive packets from said assembly buffer means (1006) and said global store means (1004).
Claim 8
Dependent Claim
22 words
The system of claim 7 wherein said selector means (1016) further comprises selector means for outputting said packets in round robin fashion.
Claim 9
Dependent Claim
22 words
The system of claim 7 wherein said second busses have a second number of bits larger than said first number of bits;
Claim 10
Dependent Claim
189 words
A cluster connected multiprocessing system comprising: a first plurality of processors (604), wherein each of said processing elements in said first plurality comprises a local memory; a second plurality of processors (604), wherein each of said processing elements in said second plurality comprises a local memory; first cluster controller means (602) connected to receive first data from said first plurality of processors (604), for assembling said first data into packets comprising a source field, a destination field and a command field, and for outputting said first plurality of packets; second cluster controller means (602) connected to receive second data from said second plurality of processors (604), for assembling said second data into packets comprising a source field, a destination field and a command field, and for outputting said packets; and switching network means (606) connected to receive said packets from said first and second cluster controller means (602), for decoding said destination field and for determining which one of said cluster controller means is connected to an addressed processors corresponding to said decoded destination field and for routing said packets to said one of said cluster controller means (602).
Claim 11
Dependent Claim
25 words
The system of claim 10 wherein said first and second cluster controller means (602) each comprise means for outputting said packets in round robin fashion.
Claim 12
Dependent Claim
37 words
The system of claim 10 wherein each of said processors (604) in said first and second plurality comprises means for providing direct access to said local memory by every other processor in said first and second plurality.
Claim 13
Dependent Claim
51 words
The system of claim 10, further comprising: host adaptor means (1700), for coupling a host processor to said switching network means, said host adaptor means comprising: means (1714) for receiving a set of commands from said host processor; and means (1710) for distributing said commands among a plurality of said processors.
Claim 14
Dependent Claim
42 words
The system of claim 13 wherein said host adaptor means further comprises: means (1706) for translating first memory addresses from said host processor to a band of second memory addresses in a local memory within each of said plurality of said processors.
Claim 15
Dependent Claim
19 words
The system of claim 14 wherein each of said processors comprises a general purpose processor and a database accelerator.
Claim 16
Dependent Claim
17 words
The system of claim 15 wherein at least one of said database accelerators is a sort coprocessor.
Claim 17
Dependent Claim
164 words
A cluster controller (602) for use in a multiprocessor system comprising a plurality of processing element clusters coupled by way of a switching network (606), said cluster controller (602) comprising: switching means (1002), connected to receive packets from said switching network (606), for distributing said packets from said switching network (606) in accordance with a destination address; queue means (1008), coupled to a plurality of said processing elements (604), for buffering packet flow to said plurality of processing elements, said queue means comprising a plurality of packet queues associated with each of said processing elements, assembly buffer means (1006), coupled to said plurality of said processing elements (604), for assembling data from said processing elements (604) into packets, said assembly buffer means (1006) comprising one assembly buffer (1014) for each of said processing elements (604); and selector means (1016), coupled to said assembly buffer means (1006) for selecting a packet from said assembly buffer means (1006) to be sent to said switching network (606).
Claim 18
Dependent Claim
182 words
A packet format for use in a cluster connected multiprocessing system comprising: a command field comprising: a first defined pattern of bits which when decoded by a cluster controller within said multiprocessing system will cause a write to a global memory within said cluster controller; a second defined pattern of bits which identifies a packet including said command field as carrying a message body; a third defined pattern of bits which identifies a packet including said command field as carrying a message header; a sequence number field for carrying any of a sequence number of a packet where said command field defines said packet as a message body, and a count of message packets to follow where said command field defines said packet as a message header; a destination field for carrying an first address of a destination processing element in said cluster connected multiprocessing system; a source field for carrying a second address of a source processing element in said cluster connected system; a data field; and an error correction code field for carrying an error correct, error detect correction code.
Claim 19
Dependent Claim
41 words
The packet format of claim 18, wherein said command field further comprises a fourth defined pattern of bits which when decoded by said cluster controller will cause a local memory in a processor connected to said cluster controller to be accessed.
References Cited (Backward Citations)
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