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EP0447225A2 Expired / Lapsed EP ⏱️ 0.0 years remaining

Methods and apparatus for maximizing column address coherency for serial and random port accesses in a frame buffer graphics system

Assignee: HP Inc
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Filing: 1991-03-14
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Granted: —
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Expires: 2011-03-14
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Abstract

Abstract Methods and apparatus for maximizing column address coherency for serial (S) and random port (P) accesses in dual port frame buffer graphics systems. With the use of methods and apparatus provided in accordance with the present invention, processing time is greatly reduced while system performance is enhanced for DMA transfer of data in graphic systems. The methods comprise the steps of organizing the video random access arrays into tiles (A0-D3), and shifting scan line data at fixed intervals across a video display (80). Graphics display systems adapted to provide high performance page mode operation comprising raster scan display means (80) having a plurality of scan lines for displaying graphics images, frame buffer means (60) interfaced with the raster scan display means (80) for mapping pixel value data corresponding to graphics primitives on the display means (80), the frame buffer means (60) being organized into a plurality of rows and columns (A0-D3), random port means (R) interfaced with the frame buffer means (60) for outputting scan line data to the raster scan display means (80) corresponding to the pixel value data of graphics primitives, serial port means (S) interfaced with the frame buffer means (60) for outputting scan line data to the raster scan display means (80) and refreshing the raster scan display means (80) with the pixel value data, and barrel shifting means (90) interfaced with the serial port means (S) for shifting the scan lines at a fixed interval so that the frame buffer (60) partially outputs scan line data to the raster scan display means (80) are also provided.

Inventors

  • 👤 Desi Rhoden
  • 👤 Darel N. Emmot

Bibliographic Details

Application Number —
Jurisdiction EP
Data Source google_patents
Last Synchronized 2026-10-30 12:21
CPC Classifications
G; G09; G09G; G09G5/00; G09G5/36; G09G5/39

Claims Analysis

Total Claims: 10
Claim 1
Independent Claim 81 words
A method of maximizing column address coherency for serial and random port accesses in a video random access memory (VRAM) array frame buffer (60) which utilizes a raster scan device (80) to display graphics primitives comprising the steps of: organizing the VRAM array into tiles (A0-D3); and shifting scan line data at a fixed interval across the raster scan display (80) so that portions of scan line data are output to the raster scan device (80) to display the graphics primitives.
Claim 2
Dependent Claim 106 words
The method recited in claim 1 wherein the shifting step comprises the steps of: addressing a first scan line with a first specified row in the frame buffer (60); addressing at least one other scan line with a second specified row in the frame buffer (60), wherein the second specified row in the frame buffer (60) is a multiple of the first specified row and wherein each row contains a plurality of columns; and outputting scan line data to the raster scan display (80) from the first and second specified rows in the frame buffer at a fixed interval determined according to the plurality of columns.
Claim 3
Dependent Claim 42 words
The method recited in claim 2 wherein the outputting step comprises the step of barrel shifting (250) the first and second scan lines so that the output data from the first and second scan lines can be switched at the fixed interval.
Claim 4
Dependent Claim 19 words
The method recited in claim 3 wherein the tiles (A0-D3) are organized into four by four blocks of VRAMs.
Claim 5
Dependent Claim 119 words
The method recited in claim 4 further comprising the steps of: addressing a third scan line with a third specified row of VRAMs in the frame buffer (60), wherein the third specified row of VRAMs in the frame buffer (60) is a multiple of the first specified row; addressing a fourth scan line with a fourth specified row of VRAMs in the frame buffer (60), wherein the fourth specified row of VRAMs in the frame buffer (60) is a multiple of the first specified row; and outputting scan line data to the raster scan display (80) from the third and fourth specified rows in the frame buffer (60) at the fixed interval determined according to the plurality of columns.
Claim 6
Dependent Claim 20 words
The method recited in claim 5 wherein the fixed interval determined according to the plurality of columns follows the relationship:
Claim 7
Independent Claim 168 words
A method of displaying data on a raster scan display device (80) in a frame buffer graphics system, wherein the frame buffer (60) has a serial port (S) and a random port (R) comprising the steps of: organizing the frame buffer (60) into a plurality of multidimensional graphics tiles (A0-D3); addressing a first scan line with a first specified row of video random access memory (VRAM) chips in a VRAM bank, wherein the first row (A) comprises a plurality of columns (A0-A3); addressing at least one other scan line with a second specified row of VRAM chips in the VRAM bank, wherein the second specified row (B) is a multiple of the first specified row (A); and outputting scan line data from the serial port (S) of the frame buffer (60) to the raster scan display (80) at a fixed interval determined according to a plurality of columns in the first specified row (A), thereby outputting portions of scan line data from the first and second scan lines.
Claim 8
Dependent Claim 174 words
A graphics display system adapted to provide high performance page mode operation comprising: raster scan display means (80) having a plurality of scan lines (A-D) for displaying graphics images; frame buffer means (60) interfaced with the raster scan display means (80) for mapping pixel value data corresponding to graphics primitives on the display means (80), the frame buffer means (60) being organized into a plurality of rows and columns (A0-D3); random port means interfaced with the frame buffer means (60) for accessing the pixel value data and storing the pixel value data on the frame buffer means; serial port means interfaced with the frame buffer means (60) for outputting scan line data to the raster scan display means (80) and refreshing the raster scan display means (80) with the pixel value data; and barrel shifting means (90) interfaced with the serial port means and random port means for shifting the scan lines at a fixed interval so that the frame buffer (60) partially outputs scan line data to the raster scan display means (80).
Claim 9
Dependent Claim 33 words
The graphics display system recited in claim 8 wherein the frame buffer means (60) comprises a plurality of video random access memory (VRAM) chips organized into the plurality of rows and columns (A0-D3).
Claim 10
Dependent Claim 25 words
The graphics display system recited in claim 9 wherein the fixed interval corresponds to an integral multiple of the number of columns in the rows.

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