Patent EP0457345A2 successfully refreshed from Google Patents.
EP0457345A2
Expired / Lapsed
EP
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Information processing apparatus
Assignee: NEC Corp
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Filing: 1991-05-17
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Granted: —
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Expires: 2011-05-17
Abstract
Abstract An information processing apparatus includes a plurality of processors, a memory unit, a plurality of address conversion tables, an address conversion table managing unit, an address conversion table control unit, a processor managing unit, and an abnormality processing unit. The processors perform arithmetic operations for information processing. The memory unit is accessed commonly by the processors. The address conversion tables convert a logic address into a physical address. The address conversion table managing unit has directories for managing the address conversion tables in accordance with contents of the logic address and Nos. of processors accessible to the address conversion tables. The address conversion table control unit updates the address conversion table managing unit to update contents of the address conversion tables. The processor managing unit checks whether each processor is operable. The abnormality processing unit performs processing for deleting a specific processor No. from a directory of the address conversion table managing unit in accordance with abnormality information from the processors.
Inventors
- 👤 Yoshifumi c/o NEC Corporation Fujiwara
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-05 06:40
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/0223; G06F12/0284; G06F11/00; G06F11/07; G06F11/0703; G06F11/0706; G06F11/0721; G06F11/0724; G06F11/0793; G06F7/00
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
160 words
An information processing apparatus comprising: a plurality of processors (24 - 27) for performing arithmetic operations for information processing; a memory unit (1) to be accessed commonly by said processors (24 - 27); a plurality of address conversion tables (16 - 19) for converting a logic address into a physical address; address conversion table managing means having directories (4 - 7) for managing said address conversion tables (16 - 19) in accordance with contents of said logic address and Nos. of processors accessible to said address conversion tables (16 - 19); address conversion table control means for updating said address conversion table managing means to update contents of said address conversion tables (16 - 19); processor managing means (28) for checking whether each processor is operable; and abnormality processing means for performing processing for deleting a specific processor No. from a directory of said address conversion table managing means in accordance with abnormality information from said processors (24 - 27).
Claim 2
Dependent Claim
78 words
An apparatus according to claim 1, wherein said abnormality processing means comprises forced clear designating means for designating one of operable processors designated by said processor managing means (28) to delete the specific processor No. from said address conversion table managing means, and forced control means of said operable processors, for sending the specific processor No. and a directory clear request to said address conversion table control means in accordance with the designation from said forced designating means.
Claim 3
Dependent Claim
89 words
An apparatus according to claim 1 or 2, further comprising a system control processor (29) for managing the entire system, and wherein said abnormality processing means comprises forced clear designating means for designating said system control processor (29) to delete the specific processor No. from said address conversion table managing means, and forced control means of said system control processor (29), for sending the specific processor No. and a directory clear request to said address conversion table control means in accordance with the designation from said forced designating means.
Claim 4
Dependent Claim
49 words
An apparatus according to claim 1, wherein said abnormality processing means comprises forced control means of said processor managing means, for receiving abnormality information from said processors (24 - 27) and sending the specific processor No. and a directory clear request directly to said address conversion table control means.
Claim 5
Independent Claim
45 words
An apparatus according to any one of claims 1 to 4, wherein said logic address is constituted by a partial space No., a page No., and an intrapage address, and said directories (4 - 7) manage said address conversion tables using said partial space Nos.
Claim 6
Independent Claim
41 words
An apparatus according to any one of claims 1 to 5, wherein the No. of said accessible processor is constituted by accessible processor designation bits, and said directories (4 - 7) manage said address conversion tables using the partial space Nos.
Claim 7
Independent Claim
29 words
An apparatus according to any one of claims 1 to 6, wherein said directories (4 - 7) are provided in correspondence with said address conversion tables (16 - 19).
Claim 8
Dependent Claim
235 words
An information processing apparatus comprising; a plurality of processors (24 - 27) for performing arithmetic operations for information processing; a memory unit (1) to be commonly accessed by said processors (24 - 27); a plurality of address conversion tables (16 - 19) for converting a logic address constituted by a partial space No., a page No., and an intrapage address into a physical address; address conversion table managing means including directories (4 - 7) in correspondence with said address conversion tables (16 - 19), said directories (4 - 7) managing said address conversion tables (16 - 19) in accordance with the partial space No. of said logic address and an accessible processor designation bit indicating a processor accessible to said address conversion tables (16 - 19); address conversion table control means for updating said address conversion table managing means to update contents of said address conversion tables (16 - 19); processor managing means (28) for checking whether each processor is operable; forced clear designating means for designating one of said accessible processors designated by said processor managing means (28) to delete a specific processor No. from said address conversion table managing means in accordance with abnormality information from said processors; and forced control means for causing one of said operable processors to issue a directory clear request to said address conversion table control means in accordance with the designation from said forced clear designating means.
Claim 9
Dependent Claim
244 words
An information processing apparatus comprising: a plurality of processors (24 - 27) for performing arithmetic operations for information processing; a memory unit (1) to be commonly accessed by said processors (24 - 27); a plurality of address conversion tables (16 - 19) for converting a logic address constituted by a partial space No., a page No., and an intrapage address into a physical address; address conversion table managing means having directories (4 - 7) in correspondence with said address conversion tables (16 - 19), said directories managing said address conversion tables by a partial space No. of said logic address and an accessible processor designation bit indicating processors accessible to said address conversion tables (16 - 19); address conversion table control means for updating said address conversion table managing means to update contents of said address conversion tables (16 - 19); processor managing means (28) for checking whether each processor is operable; a system control processor (29) for managing the entire system; forced clear designating means for causing said processor managing means (28) to designate said system control processor (29) to delete a specific processor No. from said address conversion table managing means in accordance with abnormality information from said processors (24 - 27); and forced control means for causing said system control processor (29) to issue a directory clear request of the specific processor No. to said address conversion table control means in accordance with the designation from said forced clear designating means.
Claim 10
Dependent Claim
204 words
An information processing apparatus comprising: a plurality of processors (24 - 27) for performing arithmetic operations for information processing; a memory unit (1) to be commonly accessed by said processors; a plurality of address conversion tables (16 - 19) for converting a logic address constituted by a partial space No., a page No., and an intrapage address into a physical address; address conversion table managing means having directories (4 - 7) in correspondence with said address conversion tables (16 - 19), said directories (4 - 7) managing said address conversion tables (16 - 19) in accordance with the partial space No. of said logic address and an accessible processor designation bit indicating processors accessible to said address conversion tables (16 - 19); address conversion table control means for updating said address conversion table managing means to update contents of said address conversion tables (16 - 19); processor managing means (28) for checking whether each processor is operable; and forced control means for causing said processor managing means to issue a directory clear request for deleting a specific processor No. from said address conversion table managing means to said address conversion table control means in accordance with abnormality information from said processors (24 - 27).
References Cited (Backward Citations)
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