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EP0468818A2
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ATM cell format conversion system
Assignee: NEC Corp
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Filing: 1991-07-26
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Granted: —
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Expires: 2011-07-26
Abstract
Abstract An ATM (Asynchronous Transfer Mode) cell format conversion system writes in a memory only a plurality of ATM cells each being 53 octets long and mapped in the payload fields of virtual containers VC-4-NC which have been multiplexed in the form of STM-N frames. A 1 octet long cell overhead is added to each of the ATM cells read out of the memory in response to base frame pulses which are synchronous to the STM-N frames, whereby the ATM cells are converted to 1-octet added ATM cells each being 54 octets long. The 1-octet added ATM cells and an idle cell are mapped in an imaginary 5 column groups x 9 rows matrix frame by frame and then outputted. This allows each of the STM-N frames to be switched to otherwise processed on an ATM cell basis.
Inventors
- 👤 Hiroshi C/O Nec Corporation Yamashita
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-30 11:36
CPC Classifications
H; H04; H04J; H04J3/00; H04J3/16; H04J3/1605; H04J3/1611; H04J3/1617; H04L; H04L12/00; H04L12/54; H04L12/56; H04L12/5601; H04L49/00; H04L49/10; H04L49/104; H04L49/105; H04L49/108; H04L49/30; H04L49/3081; H04L49/60; H04L49/606; H04L2012/5672; H04L2012/5674
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
192 words
A method of converting an ATM (Asynchronous Transfer Mode) cell format, comprising the steps of: receiving a digital signal multiplexed in the form of STM (Synchronous Transfer Mode)-N frames prescribed by CCITT Recommendation G.708 and made up of a plurality of ATM cell streams each having a plurality of 53 octets long ATM cells mapped in the payload fields of virtual containers VC-4-NC and SDH (Synchronous Digital Hierarchy) overhead information consisting of path overhead (POH) information of said virtual containers VC-4-NC and section overhead (SOH) information of said STM-N frames; removing said SDH overhead information from said digital signal to extract said plurality of ATM cells; adding 1 octet long cell overhead information to each of said extracted ATM cells to convert said ATM cells to 1-octet added ATM cells each being 54 octets long; generating an idle cell which is 54 octets long; adding said idle cell to said 1-octet added ATM cells; and mapping said 1-octet added ATM cells such that a synchronous relation between said STM-N frames and said 1-octet added ATM cells accommodated in said STM-N frames and a predetermined repetition period of said STM-N frames are maintained.
Claim 2
Dependent Claim
35 words
A method as claimed in claim 1, wherein a 54 octets long control information cell is added to said 1-octet added ATM cells together with said idle cell every predetermined number of said STM-N frames.
Claim 3
Independent Claim
229 words
An apparatus for converting an ATM cell format, comprising: SDH terminating means for receiving as an input signal an ATM cell stream having a plurality of 53 octets long ATM cells mapped in the payload fields of virtual containers VC-4-NC having been multiplexed in the form of STM-N frames, and generating a payload field indication signal representative of a payload field by detecting the position of SDH overhead information associated with each of said STM-N frames; ATM cell rearranging means for removing, in response to said payload field indication signal, said SDH overhead information from said STM-N frames to extract said ATM cells, adding said cell overhead information to each of said ATM cells to convert said ATM cells to 1-octet added ATM cells each being 54 octets long, and rearranging said 1-octet added ATM cells such that a synchronous relation between said STM-N frames and said 1-octet added ATM cells accommodated in said STM-N frames and a predetermined repetition period of said STM-N frames are maintained; and idle cell inserting means for generating, when the ATM cells at the input side and the output side of said ATM cell rearranging means have a phase difference which is smaller than a predetermined value, an idle cell equal in length to said 1-octet added ATM cells and inserting said idle cell in the output of said ATM cell rearranging means.
Claim 4
Dependent Claim
64 words
An apparatus as claimed in claim 3, further comprising control information cell inserting means interposed between said ATM cell rearranging means and said idle cell inserting means for generating a control information cell equal in length to said 1-octet added ATM cells every predetermined number of said STM-N frames, and inserting said control information cell to the output of said ATM cell rearranging means.
Claim 5
Dependent Claim
333 words
An apparatus as claimed in claim 3 or 4, wherein said ATM cell rearranging means comprises: an ATM cell synchronous circuit for generating an ATM cell boundary signal in response to the boundary between nearby ones of said plurality of ATM cells accommodated in said payload field; a write cell counter for generating a write reset signal every time said write cell counter counts a predetermined number of said ATM cell boundary signals; a write address counter initialized by said write reset signal for sequentially generating write address signals by using said payload field indication signal as a count enable signal; a memory using said payload field indication signal as a write enable signal for sequentially storing, in response to said write address signals, said 53 octets long ATM cells accommodated in said payload field, and sequentially reading said stored ATM cells thereoutof in response to read address signals; a read counter for generating a read reset signal every predetermined period of time corresponding to said predetermined number of 1-octet added ATM cells on the basis of base frame pulses equal in period to said STM-N frames, and generating, when a cell of another kind is inserted in the output of said memory, a count disable signal equal in length to said 1-octet added ATM cells while delaying the next read reset signal by a period of time equal to the length of said count disable signal; a read address counter initialized by said read reset signal for sequentially generating said read address signals by repeating said predetermined number of times an operation of stopping counting by one octet every time said read address counter counts 53 octets and generating said cell overhead addition signal in response to said count disable sigal; and a selector responsive to said cell overhead addition signal for adding said cell overhead information to each of said 53 octets long ATM cells appearing on the output of said memory to thereby send out said 1-octet added ATM cells.
References Cited (Backward Citations)
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