Patent EP0468831A2 successfully refreshed from Google Patents.
EP0468831A2
Expired / Lapsed
EP
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Bus protocol for write-back cache processor
Assignee: Digital Equipment Corp
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Filing: 1991-06-26
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Granted: —
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Expires: 2011-06-26
Abstract
Abstract A pipelined CPU executing instructions of variable length, and referencing memory using various data widths. Macroinstruction pipelining is employed (instead of microinstruction pipelining), with queueing between units of the CPU to allow flexibility in instruction execution times. A wide bandwidth is available for memory access; fetching 64-bit data blocks on each cycle. A hierarchical cache arrangement has an improved method of cache set selection, increasing the likelihood of a cache hit. A writeback cache is used (instead of writethrough) and writeback is allowed to proceed even though other accesses are suppressed due to queues being full. If a non-recoverable error detected by ECC circuits in the cache, an error transition mode is entered wherein the cache operates under limited access rules, allowing a maximum of access by the system for data blocks owned by the cache, but yet minimizing changes to the cache data so that diagnostics may be run. Separate queues are provided for the return data from memory and cache invalidates, yet the order or bus transactions is maintained by a pointer arrangement. The bus protocol used by the CPU to communicate with the system bus is of the pended type, with transactions on the bus identified by an ID field specifying the originator, and arbitration for bus grant goes one simultaneously with address/data transactions on the bus.
Inventors
- 👤 Rebecca Stamm
- 👤 John Edmondson
- 👤 David Archer
- 👤 Samyojita Nadkami
- 👤 Raymond Strouble
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-29 11:38
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0804; G06F12/0806; G06F12/0811; G06F12/0815; G06F12/0831; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3836; G06F9/3838; G06F9/3854; G06F9/3856; G06F9/3858; F; F02; F02B; F02B75/00; F02B75/02; F02B2075/022; F02B2075/025
Claims Analysis
Total Claims: 38
Claim 1
Independent Claim
81 words
A method of operating a processor having a writeback cache, comprising the steps of: storing outgoing non-writeback transactions in a first queue, and storing outgoing writeback transactions from said cache in a second queue; issuing non-writeback transactions and writeback transactions by said processor onto a bus from said first and second queues; upon receiving a writeback-only signal from said bus, suppressing issue of said non-writeback transactions from said first queue but continuing to issue said writeback transactions from said second queue.
Claim 2
Dependent Claim
21 words
A method according to claim 1 wherein said non-writeback transactions include reads and writes to a memory connected to said bus.
Claim 3
Dependent Claim
21 words
A method according to claim 2 wherein said reads and writes are issued when a cache miss occurs in said cache.
Claim 4
Dependent Claim
33 words
A method according to claim 1 wherein said writeback transactions are writes to a memory of data from said cache with ownership of said data being transferred from said cache to said memory.
Claim 5
Dependent Claim
34 words
A method according to claim 4 wherein one of said writeback transactions occurs if another processor attempts to issue a read transaction to a location in said memory for which said cache asserts ownership.
Claim 6
Dependent Claim
14 words
A method according to claim 1 wherein said bus is a multiplexed address/data bus.
Claim 7
Dependent Claim
47 words
A method according to claim 1 wherein said cache is a multiple-level cache including a primary cache and a backup cache, said backup cache containing a subset of the data in said memory and said primary cache containing a subset of the data in said backup cache.
Claim 8
Independent Claim
138 words
A method of operating a processor having a cache and connected by a bus to a memory, comprising the steps of: storing outgoing non-writeback transactions in a first queue, and storing outgoing writeback transactions from a cache in a second queue; issuing non-writeback transactions and writeback transactions by said processor onto said bus from said first and second queues; storing incoming cache coherency transactions in a third queue until the transactions can be implemented in the cache; when said third queue is full, asserting a suppress signal by said processor to said bus to surpress certain further cache coherency transactions from being sent to said processor until said third queue is no longer full; upon receiving a writeback-only signal from said bus, suppressing issue of said non-writeback transactions from said processor but continuing to issue said writeback transactions.
Claim 9
Dependent Claim
17 words
A method according to claim 8 wherein said non-writeback transactions include reads and writes to said memory.
Claim 10
Dependent Claim
21 words
A method according to claim 9 wherein said reads and writes are issued when a cache miss occurs in said cache.
Claim 11
Dependent Claim
33 words
A method according to claim 8 wherein said writeback transactions are writes to said memory of data from said cache with ownership of said data being transferred from said cache to said memory.
Claim 12
Dependent Claim
42 words
A method according to claim 11 including the steps of issuing read and write transactions from another processor to said memory, said cache coherency transactions invalidating data in said cache upon occurrence of a write to said memory from said another processor.
Claim 13
Dependent Claim
35 words
A method according to claim 12 wherein one of said writeback transactions occurs if said another processor attempts to issue a read transaction to a location in said memory for which said cache asserts ownership.
Claim 14
Dependent Claim
14 words
A method according to claim 8 wherein said bus is a multiplexed address/data bus.
Claim 15
Dependent Claim
47 words
A method according to claim 8 wherein said cache is a multiple-level cache including a primary cache and a backup cache, said backup cache containing a subset of the data in said memory and said primary cache containing a subset of the data in said backup cache.
Claim 16
Independent Claim
101 words
A method of operating a processor having a cache, comprising the steps of: issuing non-writeback transactions and writeback transactions by said processor onto a bus; storing incoming cache coherency transactions in a queue until the transactions can be implemented in the cache; when said queue is full, asserting a suppress signal by said processor to said bus to surpress certain further cache coherency transactions from being sent to said processor until said queue is no longer full; upon receiving a writeback-only signal from said bus, suppressing issue of said non-writeback transactions from said processor but continuing to issue said writeback transactions.
Claim 17
Dependent Claim
21 words
A method according to claim 16 wherein said non-writeback transactions include reads and writes to a memory connected to said bus.
Claim 18
Dependent Claim
21 words
A method according to claim 17 wherein said reads and writes are issued when a cache miss occurs in said cache.
Claim 19
Dependent Claim
28 words
A method according to claim 16 wherein said writeback transactions are writes of data from said cache with ownership of said data being transferred away from said cache.
Claim 20
Dependent Claim
46 words
A method according to claim 19 including the steps of issuing read and write transactions from another processor to a memory connected to said bus, said cache coherency transactions invalidating data in said cache upon occurrence of a write to said memory from said another processor.
Claim 21
Dependent Claim
35 words
A method according to claim 20 wherein one of said writeback transactions occurs if said another processor attempts to issue a read transaction to a location in said memory for which said cache asserts ownership.
Claim 22
Dependent Claim
14 words
A method according to claim 16 wherein said bus is a multiplexed address/data bus.
Claim 23
Dependent Claim
47 words
A method according to claim 16 wherein said cache is a multiple-level cache including a primary cache and a backup cache, said backup cache containing a subset of the data in said memory and said primary cache containing a subset of the data in said backup cache.
Claim 24
Dependent Claim
76 words
A processor having a writeback cache, comprising: a first queue storing outgoing non-writeback transactions, and a second queue storing outgoing writeback transactions from said cache; means for issuing non-writeback transactions and writeback transactions by said processor onto a bus from said first and second queues; means for suppressing issue of said non-writeback transactions from said first queue but continuing to issue said writeback transactions from said second queue, upon receiving a writeback-only signal from said bus.
Claim 25
Dependent Claim
21 words
A processor according to claim 24 wherein said non-writeback transactions include reads and writes to a memory connected to said bus.
Claim 26
Dependent Claim
21 words
A processor according to claim 25 wherein said reads and writes are issued when a cache miss occurs in said cache.
Claim 27
Dependent Claim
33 words
A processor according to claim 24 wherein said writeback transactions are writes to a memory of data from said cache with ownership of said data being transferred from said cache to said memory.
Claim 28
Dependent Claim
43 words
A processor according to claim 27 including another processor connected to said bus, and wherein one of said writeback transactions occurs if said another processor attempts to issue a read transaction to a location in said memory for which said cache asserts ownership.
Claim 29
Dependent Claim
14 words
A processor according to claim 24 wherein said bus is a multiplexed address/data bus.
Claim 30
Dependent Claim
47 words
A processor according to claim 24 wherein said cache is a multiple-level cache including a primary cache and a backup cache, said backup cache containing a subset of the data in said memory and said primary cache containing a subset of the data in said backup cache.
Claim 31
Independent Claim
136 words
A method of operating a processor having a bus connected to a memory, comprising the steps of: issuing a write transaction for transferring a block of data from said processor to said memory via said bus, said block of data containing a plurality of separate sub-blocks of data, said sub-blocks being applied to said bus in successive cycles of said bus; testing for errors in each sub-block of data before applying a sub-block to said bus; issuing a write command on said bus each cycle when one of said sub-blocks of data is applied to said bus which said testing indicates the data has no error; or issuing a bad-data command on said bus each cycle when one of said sub-blocks of data is applied to said bus which said testing indicates the data has errrors.
Claim 32
Dependent Claim
22 words
A method according to claim 31 wherein said block of data is a hexaword, and said sub-block of data is a quadword.
Claim 33
Dependent Claim
19 words
A method according to claim 31 wherein said block of data is stored in a cache in said processor.
Claim 34
Dependent Claim
14 words
A method according to claim 31 wherein said bus is a multiplexed address/data bus.
Claim 35
Dependent Claim
144 words
A processor system having a bus connected to a memory, comprising: write means in said processor issuing a write transaction for transferring a block of data from said processor to said memory via said bus, said block of data containing a plurality of separate sub-blocks of data, said sub-blocks being applied to said bus in successive cycles of said bus; means in said processor for testing the validity of each sub-block of data before applying a sub-block to said bus; means for issuing a write command on said bus each cycle when one of said sub-blocks of data is applied to said bus which said testing indicates the data is valid, or, alternatively for issuing a bad-data command on said bus each cycle when one of said sub-blocks of data is applied to said bus which said testing indicates the data is not valid.
Claim 36
Dependent Claim
23 words
A processor system according to claim 35 wherein said block of data is a hexaword, and said sub-block of data is a quadword.
Claim 37
Dependent Claim
20 words
A processor system according to claim 35 wherein said block of data is stored in a cache in said processor.
Claim 38
Dependent Claim
15 words
A processor system according to claim 35 wherein said bus is a multiplexed address/data bus.
References Cited (Backward Citations)
No citation records indexed.
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