Patent US1954343A successfully refreshed from Google Patents.
Patent EP0472209A2 successfully refreshed from Google Patents.
EP0472209A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Semiconductor memory device having redundant circuit
Assignee: Toshiba Corp
•
Filing: 1991-08-23
•
Granted: —
•
Expires: 2011-08-23
Abstract
Abstract An output of a column redundant circuit (20) is supplied to one spare column selection line (SCDL). The spare column selection line (SCDL) is provided to select the spare column line. The column redundant circuit (20) includes four spare column decoders (21-1 to 21-4) of the same number as that of the memory cell arrays which can be selected by the column selection line supplied with an output of a partial column decoder (11), and an OR gate (22) for deriving the logical sum of outputs of the four spare column decoders (21-1 to 21-4) and supplying the same to the spare column selection line (SCDL). An output of the OR gate (22) is supplied to a logic circuit (12) together with an output of the partial column decoder (11). <IMAGE>
Inventors
- 👤 Masaki c/o Intellectual Prop. Division Ogihara
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-04 03:39
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/70; G11C29/78; G11C29/781
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
148 words
A semiconductor memory device comprising: a plurality of memory cell arrays (AL1 to AL4); a plurality of memory cell selection lines (CDL) commonly provided for said plurality of memory cell arrays; a memory cell selection line selecting circuit (CD) for receiving an address and selecting said plurality of memory cell selection lines according to the received address; a spare memory cell selection line (SCDL) used for defective memory cell compensation; and a redundant circuit (20) in which a specified memory cell selection address corresponding to a selection line included in said plurality of memory cell selection lines and associated with a defective memory cell is programmable, and which is designed to receive a memory cell selection address and a memory cell array selection address for selecting one of said plurality of memory cell arrays, and to select said spare memory cell selection line according to the received addresses.
Claim 2
Dependent Claim
139 words
A semiconductor memory device comprising: a plurality of memory cell arrays (AL1 to AL4); a plurality of column selection lines (CDL) commonly provided for said plurality of memory cell arrays; a column selection line selecting circuit (CD) for receiving an address and selecting said plurality of column selection lines according to the received address; a spare column selection line (SCDL) used for defective memory cell compensation; and a redundant circuit (20) in which a specified column selection address corresponding to a selection line included in said plurality of column selection lines and associated with a defective memory cell is programmable, and which is designed to receive a column address and a memory cell array selection address for selecting one of said plurality of memory cell arrays, and to select said spare column selection line according to the received addresses.
Claim 3
Dependent Claim
77 words
A semiconductor memory device according to claim 2, characterized in that said redundant circuit includes spare column decoders (21-1 to 21-4) of the same number as that of said memory cell arrays, receiving a column address and a memory cell array selection address and decoding the same; and a logic circuit (22) for deriving a logical sum of outputs of said plurality of spare column decoders and supplying the logical sum to said spare column selection line.
Claim 4
Dependent Claim
88 words
A semiconductor memory device according to claim 2, characterized in that said redundant circuit includes a plurality of spare row decoders (23-1, 23-2) for receiving the memory cell array selection address and decoding the same; a plurality of spare column decoders (24-1, 24-2) for receiving decoder outputs of said spare row decoders and the column address and decoding the same; and a logic circuit (22) for deriving the logical sum of outputs of said spare column decoders and supplying the logical sum to said spare column selection line.
Claim 5
Dependent Claim
42 words
A semiconductor memory device according to claim 2, characterized in that said column selection lines are commonly formed on said plurality of memory cell arrays and arranged in parallel with column lines of said memory cell arrays to select said column lines.
Claim 6
Dependent Claim
44 words
A semiconductor memory device according to claim 2, characterized in that said column selection lines are commonly formed on said plurality of memory cell arrays to select second column lines which are arranged in parallel with first column lines of said memory cell arrays.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.