Patent EP0501828A1 successfully refreshed from Google Patents.
EP0501828A1
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Method and system for a multi channel and search global position signal processor
Assignee: Texas Instruments Inc
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Filing: 1992-02-28
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Granted: —
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Expires: 2012-02-28
Abstract
Abstract There is disclosed a multi channel GPS digital signal processor on a single IC. Each channel (11,12) contains circuitry to process L1 or L2 P(Y) and C/A-code signals. In addition a search processor (123) is included to achieve fast signal acquisition. Low power adder/accumulators (3901-Fig.4) have been designed to provide for a high precision digital oscillator (103; 104) whose output is synchronous to a high speed clock. The IC contains a full low power null detector and eight correlators (111, 113, 115, 117; 112, 114, 116, 118).
Inventors
- 👤 Leonard J. Lapadula, Iii
- 👤 George W. Pawlowski
- 👤 David Rekieta
- 👤 Hugh L. Scott
- 👤 Chyi H. Lu
- 👤 John P. Volpi
- 👤 Mitchel B. Stiles
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-27 05:54
CPC Classifications
G; G01; G01S; G01S19/00; G01S19/01; G01S19/13; G01S19/24; G01S19/21; G01S19/32; G01S19/35; G01S19/37; H; H04; H04B; H04B2201/00; H04B2201/69; H04B2201/707; H04B2201/70715
Claims Analysis
Total Claims: 28
Claim 1
Independent Claim
39 words
A device for use in GPS receivers for processing of multiple digitzed satellite signals, said device comprising: multiple L1/L2 P(Y) and C/A-code channels on a single application specific integrated circuit (ASIC); and a search processor for fast signal acquisition.
Claim 2
Dependent Claim
17 words
The device set forth in claim 1 further including: circuitry for tracking said C/A and P(Y)-code simultaneously.
Claim 3
Dependent Claim
16 words
The device set forth in claim 1 further including: circuitry for processing P-code or Y-code selectively.
Claim 4
Dependent Claim
23 words
The device set forth in claim 1 wherein said Y-code is generated by a single Y-code generator common to all said multiple channels.
Claim 5
Dependent Claim
18 words
The device set forth in claim 1 further including: circuitry for selectively processing said L1 or L2 signals.
Claim 6
Dependent Claim
17 words
The device set forth in claim 1 further including: circuitry for supporting full null zone signal inputs.
Claim 7
Dependent Claim
25 words
The device set forth in claim 1 further including: a digital oscillator for providing carrier or code clock synchronous to a high frequency reference clock.
Claim 8
Dependent Claim
35 words
The device set forth in claim 1 further including: an adder/accumulator primarily for accumulating only binary multiples, said adder/accumulator including: pulse injectors operating in conjunction with a ripple counter for reducing power and gate count.
Claim 9
Dependent Claim
29 words
The device set forth in claim 1 further including: a correlator configuration using ripple counters for predetection integration and bias accumulation; and an adder for substraction of said bias.
Claim 10
Independent Claim
43 words
The method of operating a circuit in a global positioning system (GPS) receiver, said method comprising the steps of: by digital signal processing on a single integrator circuit (IC): acquiring or tracking valid P-code signals from at least one satellite of said GPS.
Claim 11
Dependent Claim
20 words
The method set forth in claim 10 wherein said acquiring or tracking step includes the step of: processing C/A code.
Claim 12
Dependent Claim
20 words
The method set forth in claim 11 wherein said tracking step includes the step of: tracking C/A and P-code simultaneously.
Claim 13
Dependent Claim
22 words
The method set forth in claim 10 wherein said acquiring or tracking step includes the step of: processing P-code or Y-code selectively.
Claim 14
Dependent Claim
20 words
The method set forth in claim 13 wherein said acquiring or tracking step includes the step of: processing multiple channels.
Claim 15
Dependent Claim
27 words
The method set forth in claim 14 wherein said Y-code on any said channel is generated by a single Y-code generator common to all said multiple channels.
Claim 16
Dependent Claim
20 words
The method set forth in claim 10 wherein said acquiring or tracking step includes the step of: processing multiple channels.
Claim 17
Dependent Claim
18 words
The method set forth in claim 10 further comprising the step of: selectively processing L1 or L2 signals.
Claim 18
Dependent Claim
40 words
The circuit for use in a global positioning system (GPS) receiver, said circuit comprising: digital signal processing (DPS) circuitry on a single integrated circuit (IC) for acquiring or tracking valid P-code signals from at least one satellite of said GPS.
Claim 19
Dependent Claim
16 words
The circuit set forth in claim 18 wherein said DSP includes circuitry for processing C/A code.
Claim 20
Dependent Claim
18 words
The circuit set forth in claim 19 wherein said DSP includes: circuitry for tracking C/A and P-code simultaneously.
Claim 21
Dependent Claim
18 words
The circuitry set forth in claim 18 wherein said DSP includes circuitry for processing P-code or Y-code selectively.
Claim 22
Dependent Claim
19 words
The circuitry set forth in claim 18 wherein said DSP includes circuitry for supporting full null zone signal inputs.
Claim 23
Dependent Claim
40 words
The circuitry set forth in claim 18 wherein said DSP further includes a digital oscillator for providing carrier or code clock synchronous to a high frequency reference clock which mostly runs at a significantly lower frequency for reduced power dissipation.
Claim 24
Dependent Claim
24 words
The circuitry set forth in claim 23 wherein said digital oscillator for carrier generation includes circuitry for selective one or two bit carrier generation.
Claim 25
Dependent Claim
39 words
The circuitry set forth in claim 18 wherein said DSP further includes: an adder/accumulator primarily for accumulating only binary multiples, said adder/accumulator including: pulse injectors operating in conjunction with a ripple counter for reduced power dissipation and gate count.
Claim 26
Dependent Claim
31 words
The circuitry set forth in claim 18 wherein said DSP further includes: a correlator configuration including ripple counters for predetection integration bias accumulation; and an adder for subtraction of said bias.
Claim 27
Dependent Claim
44 words
A digital oscillator for providing a clock synchronous to a high frequency reference, said oscillator comprising: a low frequency adder/accumulator; a carry delay circuit; a high frequency state machine; and circuitry for interactively controlling said adder/accumulator, said carry delay circuit and said state machine.
Claim 28
Dependent Claim
33 words
An adder/accumulator for low power operation comprising: an adder/accumulator primarily for accumulating only binary multiples, said adder/accumulator including: pulse injectors operating in conjunction with a ripple counter for reducing power and gate count.
References Cited (Backward Citations)
GB2153177A
Cited
EP0351156A1
Cited
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