Patent EP0501828B1 successfully refreshed from Google Patents.
EP0501828B1
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Method and system for a multi channel and search global position signal processor
Assignee: Texas Instruments Inc
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Filing: 1992-02-28
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Granted: 2000-01-12
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Expires: 2012-02-28
Abstract
No abstract record available.
Inventors
- 👤 Leonard J. Lapadula, Iii
- 👤 George W. Pawlowski
- 👤 David Rekieta
- 👤 Hugh L. Scott
- 👤 Chyi H. Lu
- 👤 John P. Volpi
- 👤 Mitchel B. Stiles
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-24 21:36
CPC Classifications
G; G01; G01S; G01S19/00; G01S19/01; G01S19/13; G01S19/24; G01S19/21; G01S19/32; G01S19/35; G01S19/37; H; H04; H04B; H04B2201/00; H04B2201/69; H04B2201/707; H04B2201/70715
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
160 words
A digital signal processing (DSP) circuit for
use in a global positioning system (GPS) receiver, said
DSP circuit comprising, on a single integrated circuit
(IC), at least one signal processing channel (A, B), said
channel (A) including circuitry means (105, 115) for
processing a code signal from a satellite of said GPS, characterized in that: Y-code generator circuitry (108) is also provided on
said single integrated circuit; said at least one signal processing channel (A, B)
includes circuitry means (105, 115) for processing at
least one of a valid P-code signal and Y-code signal from
at least one satellite of said GPS, and comprises a
multiplicity of correlators (111-118); a search processor for fast signal acquisition and
a discrete Fourier transform (DFT) module (124) for
converting integration samples from the correlators into
a multiplicity of frequency bins of sample data are
provided, the search processor being arranged to
interpolate between the frequency bins to produce a
multiplicity of additional bins.
Claim 2
Dependent Claim
16 words
A circuit as claimed in claim 1, wherein the
search processor implements a Tong detection
algorithm.
Claim 3
Dependent Claim
15 words
A circuit as claimed in any preceding claim,
including: multiple L1/L2 P(Y) and C/A-code channels.
Claim 4
Dependent Claim
16 words
A circuit as claimed in claim 3, further
including: circuitry for tracking C/A and P(Y)-code
simultaneously.
Claim 5
Dependent Claim
16 words
A circuit as claimed in claim 3, further
including: circuitry for processing P-code or Y-code
selectively.
Claim 6
Dependent Claim
24 words
A circuit as claimed in claim 3, wherein said
Y-code generator circuitry comprises a single Y code
generator common to all said multiple channels.
Claim 7
Dependent Claim
18 words
A circuit as claimed in claim 3, further
including: circuitry for selectively processing said L1
or L2 signals.
Claim 8
Dependent Claim
17 words
A circuit as claimed in claim 3, further
including: circuitry for supporting full null zone signal
inputs.
Claim 9
Dependent Claim
25 words
A circuit as claimed in claim 3, further
including: a digital oscillator for providing carrier or code
clock synchronous to a high frequency reference clock.
Claim 10
Dependent Claim
35 words
A circuit as claimed in claim 3, further
including: an adder/accumulator primarily for accumulating only
binary multiples, said adder/accumulator including: pulse injectors operating in conjunction with a
ripple counter for reducing power and gate count.
Claim 11
Dependent Claim
29 words
A circuit as claimed in claim 3, further
including: a correlator configuration using ripple counters for
predetection integration and bias accumulation; and an
adder for subtraction of said bias.
Claim 12
Dependent Claim
176 words
A circuit as claimed in claims 2 and 3
including: two P(Y) and C/A-code channels; support circuitry means for processing null zone
signals; and wherein said channels each comprise: a carrier generator; a code clock generator; a P-code generator; a C/A-code generator; eight predetection integration accumulators; and
a noise meter; said search processor comprising: a discrete fourier transform circuit; first circuitry means for performing frequency bin
interpolation; second circuitry means for implementing a Robertson
approximation for envelope calculation; third circuitry means for implementing a Tong
detection algorithm to determine if signal is present; a threshold calculator which uses measurements from
said noise meter; fourth circuitry means for calculating a second
search threshold for the interpolated frequency bins; fifth circuitry means for advancing or retarding
code state as required during search; a mush counter which counts Tong detection
iterations for a specific code state and either forces a
new code state or stops search; and a hit counter which counts hits associated with a
specified number of discrete fourier transform cycles and
reports the most current value.
References Cited (Backward Citations)
No citation records indexed.
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