Patent EP0513764A2 successfully refreshed from Google Patents.
EP0513764A2
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EP
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Semiconductor device and method of increasing device breakdown voltage of semiconductor device
Assignee: Toshiba Corp
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Filing: 1992-05-13
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Granted: —
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Expires: 2012-05-13
Abstract
Abstract In a semiconductor device including a composite substrate formed by bonding first and second semiconductor substrates (32; 12; 43; 52) (31; 11; 41; 51) to each other through an oxide film (33a; 13a; 43a; 53a) and an insulator isolation trench (33b; 13b 43b; 53b) formed from a major surface of the first semiconductor substrate ( 32; 12; 42; 52) to reach the oxide film (33a; 13a; 43a; 53a) and to surround an element forming region, when the potential of the second substrate (31; 11; 41; 51) is set at a potential higher than the minimum potential in the element forming region of the first substrate (32; 12; 42; 52), an breakdown voltage can be increased. In a semiconductor integrated circuit having an element isolation region, a semiconductor device of a perfect dielectric isolation structure having an element forming region having a thickness smaller than that of the element forming region of a P-N junction isolation structure is used to reduce, e.g., a base curvature influence, thereby obtaining a further high breakdown voltage.
Inventors
- 👤 Yoshiro c/o Intellectual Pty. Div. Baba
- 👤 Shunichi c/o Intellectual Pty. Div. Hiraki
- 👤 Akihiko c/o Intellectual Pty. Div. Osawa
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-09 06:55
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/64; H10D30/65; H10D30/657; H10D89/00; H10D89/211; H10D89/311; H10D62/00; H10D62/10; H10D62/17; H10D62/351; H10D62/357; H10D62/364; H10D62/378; H10D89/213; Y; Y10; Y10S; Y10S257/00; Y10S257/901
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
88 words
A semiconductor device comprising: a composite semiconductor substrate (35) formed by bonding a first semiconductor substrate (32) and a second semiconductor substrate (31) through an oxide interlayer (33), said first semiconductor substrate (32) including an element forming region having a thickness and an impurity concentration such that full depletion occurs in a depletion layer; and potential setting means (34) for setting a potential of said second semiconductor substrate (31) at a potential higher than a minimum potential in said element forming region of said first semiconductor substrate (32).
Claim 2
Dependent Claim
41 words
A device according to claim 1, characterized in that said potential setting means (34) has potential fixing means for fixing a potential of said second semiconductor substrate (31) to an optimal potential value at which a maximum breakdown voltage is obtained.
Claim 3
Dependent Claim
27 words
A device according to claim 1, characterized by further comprising a predetermined semiconductor element (30) formed in said element forming region of said first semiconductor substrate (32).
Claim 4
Dependent Claim
18 words
A device according to claim 3, characterized in that said semiconductor element (30) consists of a P⁺NN⁺ diode.
Claim 5
Dependent Claim
18 words
A device according to claim 3, characterized in that said semiconductor element (30) consists of an NPN transistor.
Claim 6
Dependent Claim
18 words
A device according to claim 3, characterized in that said semiconductor element (30) consists of a CMOS inverter.
Claim 7
Dependent Claim
19 words
A device according to claim 3, characterized in that said semiconductor element (30) consists of a lateral double-diffused MOSFET.
Claim 8
Dependent Claim
18 words
A device according to claim 3, characterized in that said semiconductor element (30) consists of a lateral MOSFET.
Claim 9
Dependent Claim
124 words
A semiconductor integrated circuit device comprising: a composite semiconductor substrate (35) formed by bonding a first semiconductor substrate (32) and a second semiconductor substrate (31) through an oxide interlayer (33a), said first semiconductor substrate (32) including an element forming region having a thickness and an impurity concentration such that full depletion occurs in a depletion layer; an insulator isolation trench (33b) formed from a major surface of said first semiconductor substrate (32) to reach said oxide interlayer (33a) and to surround said element forming region and buried with an insulator; and potential setting means (34) for setting a potential of said second semiconductor substrate (31) at a potential higher than a minimum potential in said element forming region of said first semiconductor substrate (32).
Claim 10
Dependent Claim
41 words
A device according to claim 9, characterized in that said potential setting means (34) has potential fixing means for fixing a potential of said second semiconductor substrate (31) to an optimal potential value at which a maximum breakdown voltage is obtained.
Claim 11
Dependent Claim
27 words
A device according to claim 9, characterized by further comprising a predetermined semiconductor element (30) formed in said element forming region of said first semiconductor substrate (32).
Claim 12
Dependent Claim
18 words
A device according to claim 11, characterized in that said semiconductor element (30) consists of a P⁺NN⁺ diode.
Claim 13
Dependent Claim
18 words
A device according to claim 11, characterized in that said semiconductor element (30) consists of an NPN transistor.
Claim 14
Dependent Claim
18 words
A device according to claim 11, characterized in that said semiconductor element (30) consists of a CMOS inverter.
Claim 15
Dependent Claim
19 words
A device according to claim 11, characterized in that said semiconductor element (30) consists of a lateral double-diffused MOSFET.
Claim 16
Dependent Claim
17 words
A device according to claim 11, characterized in that said semiconductor element consists of a lateral MOSFET.
Claim 17
Independent Claim
171 words
A method of increasing a device breakdown voltage of a semiconductor device, comprising the steps of: determining a semiconductor substrate having a perfect dielectric isolation structure consisting of a composite semiconductor substrate (35; 15; 45; 55) formed by bonding a first semiconductor substrate (32; 12; 42; 52) and a second semiconductor substrate (31; 11; 41; 51) to each other through an oxide interlayer (33a; 13a; 43; 53a) and an insulator isolation trench (33b; 13b; 43b; 53b) formed from a major surface of said first semiconductor substrate (32; 12; 42; 52) to reach said oxide interlayer (33a; 13a; 43a; 53) and to surround said element forming region and buried with an insulator; determining a type of a semiconductor element (30) formed in said element forming region; identifying a minimum potential used in said semiconductor element (30) according to the type of said semiconductor element (30); and biasing a potential of said second semiconductor substrate (31; 11; 41; 51) to a predetermined potential higher than the minimum potential of said semiconductor element (30).
Claim 18
Dependent Claim
41 words
A method according to claim 17, characterized in that the step of biasing a potential includes the step of setting the potential of said second semiconductor substrate (31; 11; 41; 51) to an optimal potential for obtaining a maximum breakdown voltage.
Claim 19
Dependent Claim
69 words
A method according to claim 18, characterized in that the step of setting the potential of said second semiconductor substrate (31; 11; 41; 51) to an optimal potential includes the step of determining the optimal potential by a thickness and impurity concentration of said element forming region, a thickness of said oxide interlayer (33a; 13a; 43a; 53a), and a depth of a predetermined diffusion region of said semiconductor element.
Claim 20
Independent Claim
147 words
A method of determining an ON resistance of a lateral MOSFET comprising the steps of: determining a semiconductor substrate having a perfect dielectric isolation structure consisting of a composite semiconductor substrate (65) formed by bonding a first semiconductor substrate (62) and a second semiconductor substrate (61) to each other through an oxide interlayer (63a) and an insulator isolation trench (63b) formed from a major surface of said first semiconductor substrate (62) to reach said oxide interlayer 63a and to surround said element forming region and buried with an insulation; identifying a polarity of carriers in said first semiconductor substrate (62); and applying a bias voltage (V ss ) having a polarity opposite to said polarity of said carriers in said first semiconductor substrate (62) to said second semiconductor substrate (61) through said oxide interlayer 63a to thereby decrease an On resistance of said first semiconductor substrate (62).
Claim 21
Dependent Claim
50 words
A method according to claim 20, characterized in that said step of applying said bias potential (V ss ) includes the step of decreasing said ON resistance of said first semiconductor substrate (62) according to an increase of said bias voltage (V ss ) of said second semiconductor substrate (61).
Claim 22
Dependent Claim
38 words
A method according to claim 20, characterized in that said bias voltage (V ss ) of a negative polarity is applied to said second semiconductor substrate (61) when said first semiconductor substrate (62) is a P-type semiconductor substrate.
Claim 23
Dependent Claim
38 words
A method according to claim 20, characterized in that said bias voltage (V ss ) of a positive polarity is applied to said second semiconductor substrate (61) when said first semiconductor substrate (62) is on N-type semiconductor substrate.
References Cited (Backward Citations)
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