Patent US5283557A successfully refreshed from Google Patents.
Patent EP0557581A2 successfully refreshed from Google Patents.
EP0557581A2
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EP
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Non-volatile DRAM cell
Assignee: International Business Machines Corp
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Filing: 1992-10-29
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Granted: —
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Expires: 2012-10-29
Abstract
Abstract The present invention is directed to a one-transistor non-volatile DRAM cell (10, 40, 66, 79) having a two layer floating gate (14) to allow the contents of a storage capacitor (28) to be transferred to the floating gate (14) during power interruptions. The first layer (18) of the floating gate (14) is separated from a storage node (32) of the storage capacitor (28) by a tunnel oxide (92) to allow electron tunnelling between the floating gate (14) and the storage capacitor (32). In another embodiment of the present invention, a dual electron injector structure (44) is disposed between a one layer floating gate (42) and the storage node (32) to allow electrons to be injected between the floating gate (42) and the storage node (32). In another embodiment of the present invention, an erase gate (70) is implemented to remove the charge on the floating gate (14, 42). The erase gate (70) can be separated from the floating gate (14, 42) by a tunnel oxide (92) or a single electron injector structure (44) to allow electrons to travel from the floating gate (14, 42) to the erase gate (70).
Inventors
- 👤 Alexandre Acovic
- 👤 Ching-Hsiang Dep. Of Electrical Engineering Hsu
- 👤 Matthew Robert Wordeman
- 👤 Being Song Wu
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-29 10:34
CPC Classifications
B; B82; B82Y; B82Y10/00; G; G11; G11C; G11C14/00
Claims Analysis
Total Claims: 33
Claim 1
Independent Claim
208 words
A non-volatile dynamic random access memory cell (10, 66) comprising: a semiconductor substrate (16); a layer of insulating material (34, 92, 94, 100) formed on a surface (22) of said semiconductor substrate (16); a storage capacitor (28) having a storage node (32) formed in said semiconductor substrate (16); a control electrode (12) formed on a surface of said insulating layer (34); a source diffusion region (24) formed in said semiconductor substrate (16); a transfer transistor (36) disposed between said storage node (32) and said source diffusion region (24); and a floating gate (14) formed in said layer of insulating material (34) between said control electrode (12) and said surface (22) of said semiconductor substrate (16), said floating gate (14) having a first layer (18) disposed over said storage node (32) and separated therefrom by said insulating material (34, 22) having a thickness that will allow electrons to tunnel between said storage node (32) and said first layer (18) for transferring a charge directly between said floating gate (14) and said storage capacitor (28), and a second layer (20) disposed at a greater distance from said surface (22) of said semiconductor substrate (16) than said first layer (18), said first layer (18) being connected to said second layer (20).
Claim 2
Dependent Claim
27 words
The memory cell of claim 1 wherein said first layer (18) of said floating gate (14) is separated from said storage node by a tunnel oxide (92).
Claim 3
Dependent Claim
30 words
The memory cell of claim 1 wherein said first layer (18) of said floating gate (14) is separated from said storage node (32) by approximately 7nm of insulating material (34).
Claim 4
Dependent Claim
34 words
The memory cell of claim 3 wherein said second layer (18) of said floating gate (14) is separated from said surface (22) of said semiconductor substrate (16) by approximately 14nm of insulating material (34).
Claim 5
Dependent Claim
29 words
The memory cell of claim 4 wherein said control electrode is separated from said second layer (18) of said floating gate (14) by approximately 7nm of insulating material (34).
Claim 6
Dependent Claim
30 words
The memory cell of claim 1 further including an erase gate (68) formed in said layer of insulating material (34) above said first layer (18) of said floating gate (14).
Claim 7
Dependent Claim
47 words
The memory cell of claim 6 wherein said erase gate (68) is separated from said first layer (18) of said floating gate (14) by said insulating material (34) having a thickness that will allow electrons to tunnel from said first layer (18) to said erase gate (68).
Claim 8
Dependent Claim
30 words
The memory cell of claim 7 wherein said erase gate (68) is separated from said first layer (18) of said floating gate (14) by approximately 7nm of insulating material (34).
Claim 9
Dependent Claim
48 words
The memory cell of claim 6 further including a single electron injector structure (74) disposed between said erase gate (68) and said first layer (18) of said floating gate (14) for injecting electrons from the first layer (18) of the floating gate (14) to the erase gate (68).
Claim 10
Dependent Claim
149 words
A non-volatile dynamic random access memory cell (40, 79) comprising: a semiconductor substrate (16); a layer of insulating material (34, 92, 94, 100) formed on a surface (22) of said semiconductor substrate (16); a storage capacitor (28) having a storage node (32) formed in said semiconductor substrate (16); a control electrode (12) formed on a surface of said insulating layer (34); a source diffusion region (24) formed in said semiconductor substrate (16); a transfer transistor (36) disposed between said storage node (32) and said source diffusion region (24); and a floating gate (42) formed in said layer of insulating material (34) above said surface (21) of said semiconductor substrate (16), a portion of said floating gate (42) being disposed over said storage node (32) and separated therefrom by a dual electron injector structure (44) for transferring a charge directly between said floating gate (42) and said storage capacitor (32).
Claim 11
Dependent Claim
36 words
The memory cell of claim 1 or 10 wherein said storage capacitor (28) further includes a plate (30) formed in said layer of insulating material (34) above said storage node (32) and a connected contact (37).
Claim 12
Dependent Claim
29 words
The memory cell of claim 10 or 1 further including a metallic or polysilicon contact (26) connected to said source diffusion region (24) to form a bit line (BL).
Claim 13
Dependent Claim
28 words
The memory cell of claim 1 or 10 wherein said insulating material comprises a material selected from the group consisting of oxide, nitride, silicon dioxide and silicon nitride.
Claim 14
Dependent Claim
31 words
The memory cell of claim 10 wherein said dual electron injector structure (44) comprises two layers of silicon rich silicon dioxide (48, 46) separated by a layer of silicon dioxide (50).
Claim 15
Dependent Claim
28 words
The memory cell of claim 10 further including an erase gate (80) formed in said layer of insulating material (34) above said portion of said floating gate (42).
Claim 16
Dependent Claim
45 words
The memory cell of claim 15 wherein said erase gate (42) is separated from said portion of said floating gate (42) by said insulating material (34) having a thickness that will allow electrons to tunnel from said floating gate (42) to said erase gate (80).
Claim 17
Dependent Claim
41 words
The memory cell of claim 15 further including a single electron injector structure (86) disposed between said erase gate (80) and said portion of said floating gate (42) for injecting electrons from the floating gate (42) to the erase gate (80).
Claim 18
Dependent Claim
35 words
The memory cell of claim 6 or 17 wherein said single electron injector structure (74, 86) comprises a layer of silicon dioxide (78, 90) disposed on a layer of silicon rich silicon dioxide (76, 88).
Claim 19
Dependent Claim
20 words
The memory cell of claim 6 or 17 further including a metallic or polysilicon contact connected to said erase gate.
Claim 20
Dependent Claim
40 words
A non-volatile dynamic random access memory array (54) comprising; a semiconductor substrate 16; and a plurality of non-volatile dynamic random access memory cells according to claims 1 - 19 arranged in a plurality of rows and a plurality of columns.
Claim 21
Dependent Claim
44 words
The memory array 54 claim 20 further including a plurality of bit lines (BL), each one of said plurality of bit lines (BL) being coupled to the source diffusion region (24) of each row of said plurality of memory cells (10, 40, 66, 79).
Claim 22
Dependent Claim
38 words
The memory array of claim 21 further including a plurality of word lines (WL), each word line (WL) being coupled to the control electrode (12) of each column of said plurality of memory cells (10, 40, 66, 79).
Claim 23
Dependent Claim
45 words
The memory array of claim 22 further including a bit line decoder, precharge, sense amplifier and latch circuits (58) coupled to each of said plurality of bit lines (BL) and a word line decoder (56) coupled to each of said plurality of word lines (WL).
Claim 24
Independent Claim
283 words
A method for forming a non-volatile dynamic random access memory cell (10, 40, 66, 79) comprising the steps of: (a) providing a substrate (16) of a first conductivity type having first (32) and second (24) spaced diffusion regions; (b) depositing a tunnel oxide layer (92) on said substrate (16); (c) depositing a first layer of undoped polysilicon on said tunnel oxide layer (92) and implanting a dopant of said second conductivity type in said first layer of undoped polysilicon; (d) selectively removing a portion of said first layer of polysilicon such that the remaining portion forms a first polysilicon region (18) disposed above said first diffusion region (32), said first polysilicon region (18) forming a first layer of a floating gate (14); (e) depositing a first oxide layer (94) on said first polysilicon region (18) and exposed portions of said tunnel oxide layer (22); (f) forming a via (96) in said first oxide layer (94) to expose an end of said first polysilicon region (18); (g) depositing a second layer (98) of undoped polysilicon on said first oxide layer (94) and said exposed end of said first polysilicon region (18) and implanting a dopant of said second conductivity type in said second layer (98) of undoped polysilicon; (h) selectively removing a portion of said second polysilicon layer (98) such that the remaining portion contacts said first polysilicon region (18) and is disposed between said first (32) and second (24) spaced diffusion regions, said remaining portion of said second polysilicon layer (98) forming a second layer (20) of said floating gate (14); (i) depositing a second oxide layer (100) on said second polysilicon layer (98) and exposed portions of said first oxide layer (94).
Claim 25
Dependent Claim
51 words
The method of claim 24 wherein said step of selectively removing a portion of said first polysilicon layer (18) includes forming a second polysilicon region (30) spaced from said first polysilicon region (18), said second polysilicon region (30) being disposed above said first diffusion region (32) and forming a capacitor plate.
Claim 26
Dependent Claim
45 words
The method of claim 24 further including the step of forming a control gate (12) on said second oxide layer (100) over said first (18) and second (20) layers of said floating gate (14), and a metallic contact (26) to said second diffusion region (24).
Claim 27
Dependent Claim
25 words
The method of claim 24 wherein said tunnel oxide layer (22) is deposited by a high temperature post oxidation anneal of thermally grown dry oxide.
Claim 28
Dependent Claim
20 words
The method of claim 24 wherein said tunnel oxide layer (22) is deposited to a thickness of approximately 7 nm.
Claim 29
Dependent Claim
20 words
The method of claim 28 wherein said first oxide layer (94) is deposited to a thickness of approximately 7 nm.
Claim 30
Dependent Claim
20 words
The method of claim 29 wherein said second oxide layer (100) is deposited to a thickness of approximately 7 nm.
Claim 31
Dependent Claim
56 words
The method of claim 24 wherein said step of selectively removing a portion of said polysilicon layer includes forming an erase plate (70) comprised of a portion of said second polysilicon layer (98) spaced from said second layer (20) of said floating gate (14) and disposed above said first layer (18) of said floating gate (14).
Claim 32
Dependent Claim
58 words
The method of claim 31 further including the step of forming a control gate (12) on said second oxide layer (100) over said second layer (20) of said floating gate (14) and a portion of said first layer (18) of said floating gate (14), metallic contacts (26) to said second diffusion region (24) and said erase plate (70).
Claim 33
Dependent Claim
38 words
The method of claim 31 wherein said first oxide layer (94) is deposited to a thickness such that said erase gate (70) is separated from said first layer (18) of said floating gate (14) by approximately 7 nm.
References Cited (Backward Citations)
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