Patent EP0597218A1 successfully refreshed from Google Patents.
EP0597218A1
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EP
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An integrated single frame buffer memory for storing graphics and video data
Assignee: International Business Machines Corp
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Filing: 1993-09-21
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Granted: —
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Expires: 2013-09-21
Abstract
Abstract The present invention provides an integrated display system for multi-media workstations wherein graphics image and video data are merged in a single frame buffer. The integrated display system employs 3-port VRAMs with a first serial access port for display data output, and a random access port for graphics data, a second serial access for video data input. The display system includes a single frame buffer memory system for a multi-media workstation which operates compatibly with display systems and logic designed for dual frame buffer systems and it uses the 3-port VRAM in combination with a means incorporating improved input locking, video update or refresh, and encoded video data input stream.
Inventors
- 👤 Inching Chen
- 👤 Thomas Akos Horvath
- 👤 Andy Geng-Chyun Lean
- 👤 Bob Chao-Chu Liang
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-29 22:35
CPC Classifications
G; G09; G09G; G09G5/00; G09G5/36; G09G5/39; G09G5/393; G09G2340/00; G09G2340/12; G09G2340/125
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
191 words
In a multi-media display system of the type providing an integrated display of video, graphics and image data on a display monitor and including a source of digital image signals, a source of graphics signals, a processing unit having an image video processor means, a video capture means scaling means, a stored pre-programmed color index, a display unit having a graphics rasterizer means, a graphics buffer means and a three-port video random access memory structure which functions as a buffer memory; the improvement characterized in a graphics control means connected to said processing unit and said display unit for providing control signals for writing said digital image video signals into said three-port video random access memory structure and for providing control signals for writing said graphics signals into said three-port random access memory structure; and an input locking means connected to the output of said control means, including logic operator means for comparing said graphics signals to said stored pre-programmed colorindex for providing one of two lock bits in response to said comparing function wherein said lock bit is enabled for a compare occurrence and is disabled for a non-compare occurrence.
Claim 2
Dependent Claim
191 words
In a multi-media display system of the type providing an integrated display of video, graphics and image data on a display monitor and including a source of digital image signals, a source of graphics signals, a processing unit having an image video processor means, a video capture means scaling means, a stored pre-programmed color index, a display unit having a graphics rasterizer means, a graphics buffer means and a three-port video random access memory structure which functions as a buffer memory; the improvement characterized in a graphics control means connected to said processing unit and said display unit for providing control signals for writing said digital image video signals into said three-port video random access memory structure and for providing control signals for writing said graphics signals into said three-port random access memory structure; and an input locking means connected to the output of said control means, including logic operator means for comparing said graphics signals to said stored pre-programmed colorindex for providing one of two lock bits in response to said comparing function wherein said lock bit is enabled for a compare occurrence and is disabled for a non-compare occurrence.
Claim 3
Dependent Claim
136 words
A multi-media display system of the type according to claim 1 wherein said logic operator means of said input locking means includes first, second, third and fourth storage registers, said first and second storage registers containing pre-programmed color index data, a source color comparison means connected to the output of said graphics controller means and to the outputs of said first and second registers, and a multiplexer means connected to the outputs of said third storage register means and said source color comparison means, said source color comparison means being responsive to graphics data from said graphics controller means associated with an address being accessed and also responsive to said preprogrammed color index stored in said first and second storage registers for providing a 1 bit for a compare and a 0 bit for a non-compare.
Claim 4
Dependent Claim
73 words
A multi-media display system of the type according to claim 1 or 2, wherein said multiplexer means is further responsive to the output of said fourth register for providing a control signal; and wherein said multi-media display system further includes a two-port video random access memory means connected to the output of said multiplexer means of said input locking means, said two-port video random access memory means functioning as a keying buffer means.
Claim 5
Dependent Claim
84 words
A multi-media display system of the type according to claim 1, 2 or 3, wherein said fourth storage register of said logic operator means provides a first, in-band operating mode signal and a second, out-band operating mode signal to said multiplexer wherein said in-band signal provides an indirect update mechanism signal dependent on a comparison operation between graphics data and programmed transparent color data, and wherein said out-band signal provides a direct update mechanism dependent on programmed data provided from an input/output data port.
Claim 6
Dependent Claim
51 words
A multi-media display system of the type according to any one of the claims 1 to 4, wherein said lock bits are enabled and disabled in response to either said compare operation of said in-band mode or are enabled and disabled in response to said programmed data from said input/output port.
Claim 7
Dependent Claim
120 words
A multi-media display system of the type according to any one of the claims 1 to 5, further including means for connecting said two-port keying buffer random access memory and said fourth storage register to a first serial access input port of said three-port video random access memory means for providing display pixel masking indicators to said three-port video random access memory means functioning as a pixel frame buffer; wherein said source of video data is connected to a second serial access input port of said three-port video random access memory means; and wherein said output of said graphics controller means is connected to a random access input port for providing graphics data to said three-port video random access memory.
Claim 8
Dependent Claim
138 words
In a multi-media display system of the type according to any one of the claims 1 to 6, wherein said graphics controller means provides a plurality of refresh operations to said three-port video random access memory and wherein said graphics controller can be configured to provide a greater number of refreshes than there are rows requiring refresh in said three-port video random access memory; the improvement characterizer in means for detecting a refresh operation signal generated by said graphics controller in the form of a column address strobe signal occurring before a row address strobe signal, means for detecting a video update request signal from said video processor means; and means responsive to said refresh operation signal and said video update request signal for blocking said refresh operation signal and providing a video update signal in place thereof.
Claim 9
Dependent Claim
102 words
In a multi-media display system of the type according to any one of the claims 1 to 7, wherein said image video processor includes a video input memory means responsive to said video signals and containing control bits associated with synchronizing information from said video source, a flip-flop means responsive to the systems horizontal and vertical sync pulses, said flip-flop providing a first control bit in response to said horizontal sync pulse for indicating the status of a video scanline and for providing a second control bit in response to said vertical sync pulse for indicating the status of a video frame.
Claim 10
Dependent Claim
114 words
In a multi-media display system of the type according to any one of the claims 1 to 8, responsive to said first and second bits from said flip-flop means for providing a signal indicating a sequence change and a frame change respectively, said sequence change signal providing a first memory request signal to said three-port video random access memory for writing a line, and said frame change signal providing a second memory request signal to the system memory controller of said processing unit wherein said pair of first and second memory request signals provide an indicator signal to cause an update cycle instead of a refresh cycle to said three-port video random access memory.
References Cited (Backward Citations)
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