A method for forming a bump electrode structure of a semiconductor device

Assignee: Casio Computer Co Ltd

•

Filing: 1988-11-17

•

Granted: —

•

Expires: 2008-11-17

📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract A method for forming a bump electrode structure of a semiconductor device having an increased bonding strength per unit area. In order to achieve such an increased bonding strength per unit area, the method comprises a process for forming an under-bump layer (15) over one entire surface of the semiconductor device which has an electrode pad (13) and an insulating layer (14) covering the periphery of the electrode pad, and a process for forming the bump electrode (16) on that portion of the under-bump layer (15) opposing said electrode pad (13) which is characterised by a reactive ion sputter etching process for removing said under-bump layer (15) on the insulating surface (14) and forming fine V-shaped grooves (19) on the top surface of the bump electrode (16).

Inventors

👤 Takeshi C/O Hamura R & D Ctr Casio Wakabayashi
👤 Akira C/O Hamura R & D Center Casio Suzuki
👤 Shigeru C/O Hamura R & D Center Casio Yokoyama

Bibliographic Details

Application Number —

Jurisdiction EP

Data Source google_patents

Last Synchronized 2026-10-28 08:29

CPC Classifications

H; H10; H10W; H10W72/00; H10W72/01; H10W72/012; H10W72/20; H10W72/01231; H10W72/01233; H10W72/01235; H10W72/01251; H10W72/01253; H10W72/251; H10W72/252; H10W72/01255; H10W72/019; H10W72/01951; H10W72/01953; H10W72/231; H10W72/234; H10W72/29; H10W72/90; H10W72/921; H10W72/923; H10W72/951; H10W72/952; Y; Y10; Y10S; Y10S148/00; Y10S148/131

Claims Analysis

Total Claims: 6

Claim 1

Independent Claim 103 words

A method for forming a bump electrode (16) of a semiconductor device comprising: a process for forming an under-bump layer (15) over one entire surface of the semiconductor device which has an electrode pad (13) and an insulating layer (14) covering the periphery of the electrode pad (13); and a process for forming the bump electrode (16) on that portion of the under-bump layer (15) opposing said electrode pad (13) characterised by a reactive-ion sputter etching process for removing said under-bump layer (15) on the insulating layer (14) and forming fine V-shaped grooves (19) on the top surface of the bump electrode (16).

Claim 2

Dependent Claim 39 words

The method for forming a bump electrode (16) of a semiconductor device according to claim 1, characterised in that , a reactive-ion gas used for said reactive-ion sputter etching is a gas mixture of halide gas and chlorine-based gas.

Claim 3

Dependent Claim 22 words

The method for forming a bump electrode of a semiconductor device according to claim 2, characterised in that said gas contains SF₆.

Claim 4

Dependent Claim 22 words

The method for forming a bump electrode of a semiconductor device according to claim 2, characterised in that said gas contains CFCl₃.

Claim 5

Dependent Claim 69 words

The method for forming a bump electrode (16) of a semiconductor device according to claim 1, characterised in that said bump electrode (16) forming process includes steps of applying a wet resist to the surface of the under-bump layer (15), forming an opening (14a) in that protion of the wet resist facing the electrode pad (13) by etching, and forming the bump electrode (16) inside the opening by plating.

Claim 6

Dependent Claim 46 words

The method for forming a bump electrode of a semiconductor device according to claim 5, characterised in that the outer peripheral edge of said opening (14a) is situated inside that of said electrode pad (13), and said bump electrode (16) is thinner than the wet resist.

References Cited (Backward Citations)

No citation records indexed.

USPTO Annuity & Maintenance Windows

Maintenance schedule is calculated for granted US utility patents.

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag

Select Category

Notes (Optional)