EP0613089A1
Expired / Lapsed
EP
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Content addressable memory having memory cells storing don't care states for address translation
Assignee: Digital Equipment Corp
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Filing: 1994-02-11
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Granted: —
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Expires: 2014-02-11
Abstract
Abstract A content addressable memory has a pair of single-bit memory cells (61,63) together storing two bits of information representing either an invalid state, a logic zero state, a logic one state, or a don't care state. Each of the memory cells has a pair of transistors (133,134). One of the transistors (133) connects a common node (135) to a respective one of the address lines (141), and another of the transistors (134) connects the common node to a potential of a predefined logic level. Each of the transistors has a gate receiving a logic level of the bit of information stored in the memory cell so that one of the transistors is conductive in response to the logic level of the bit of the information when the other of the transistors is not conductive in response to the logic level of the bit of information. Each of the memory cells also includes a transistor (136) connected to the match line and having a gate connected to the common node. The content addressable memory is especially adapted for use in a translation buffer providing variable page granularity. The don't care states permit multiple virtual page numbers to match a single entry storing information for multiple physical pages. The invalid state eliminates the need for a dedicated valid bit in each entry.
Inventors
- 👤 Edward J. Mclellan
- 👤 Bruce A. Gieseke
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-08 20:26
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/10; G06F12/1027; G11; G11C; G11C15/00; G11C15/04; G06F2212/00; G06F2212/65; G06F2212/652
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
332 words
A method of accessing a memory with a one-bit signal, said memory having a pair of single-bit storage locations together storing two bits of information representing either an invalid state, a logic zero state, a logic one state, or a don't care state; said method comprising the steps of: a) storing information in said storage locations representing said invalid state, generating a signal indicating an absence of a match when said one-bit signal represents a logic zero and said information in said storage locations represents said invalid state, and generating a signal indicating an absence of a match when said one-bit signal represents a logic one and said information in said storage locations represents said invalid state; b) storing information in said storage locations representing said logic zero state, generating a signal indicating a presence of a match when said one-bit signal represents a logic zero and said information in said storage locations represents said logic zero state, and generating a signal indicating an absence of a match when said one-bit signal represents a logic one and said information in said storage locations represents said logic zero state; c) storing information in said storage locations representing said logic one state, and generating a signal indicating an absence of a match when said one-bit signal represents a logic zero and said information in said storage locations represents said logic one state, and generating a signal indicating a presence of a match when said one-bit signal represents a logic one and said information in said storage locations represents said logic one state; and d) storing information in said storage locations representing said don't care state, generating a signal indicating a presence of a match when said one-bit signal represents a logic zero and said information in said storage locations represents said don't care state, and generating a signal indicating a presence of a match when said one-bit signal represents a logic one and said information in said storage locations represents said don't care state.
Claim 2
Dependent Claim
31 words
A method as claimed in claim 1, further comprising the steps of precharging a match line, and discharging the match line whenever generating a signal indicating an absence of a match.
Claim 3
Dependent Claim
64 words
A method as claimed in claim 1 or 2, which includes the steps of complementing said one-bit signal to produce a complemented bit signal, comparing said one-bit signal to a single bit of information stored in one of said single-bit storage locations, and comparing said complemented bit signal to a single bit of information stored in another one of said single bit storage locations.
Claim 4
Dependent Claim
61 words
A method as claimed in claim 1,2 or 3, wherein said step of storing information in said storage locations representing said invalid state includes the step of asserting a flush signal on a flush line to render conductive a respective transistor for each of said single-bit storage locations to set each of said single-bit storage locations to a predetermined logical value.
Claim 5
Dependent Claim
47 words
A method as claimed in claim 1,2,3 or 4, wherein said step of storing information in said storage locations representing said don't care state includes masking a data bit with a mask bit to produce a result that is stored in one of said single-bit storage locations.
Claim 6
Dependent Claim
193 words
A content addressable memory for storing information including a "don't care" state, comparing the stored information to address signals asserted on a pair of address lines, and asserting a match signal on a match line when the stored information matches address information asserted on said address lines; said content addressable memory comprising: a pair of memory cells, each of said memory cells storing a respective bit of said stored information; each of said memory cells including: a pair of transistors, one of said transistors connecting a common node to a respective one of said address lines, another of said transistors connecting said common node to a potential of a predefined logic level, each of said transistors having a gate receiving a logic level of said bit of information stored in said each of said memory cells so that one of said transistors is conductive in response to said logic level of said bit of said information when the other of said transistors is not conductive in response to said logic level of said bit of information; and a transistor connected to said match line and having a gate connected to said common node.
Claim 7
Dependent Claim
50 words
A content addressable memory as claimed in claim 6, wherein said potential of a predefined logic level is ground potential of a semiconductor substrate including semiconductor material of said transistors, further comprising an address bit generator connected to said address lines to assert complementary address signals on said address lines.
Claim 8
Dependent Claim
250 words
A content addressable memory as claimed in claim 6 or 7, wherein each of said memory cells further comprises a transistor having a gate connected to a flush line for setting, in response to a flush signal on said flush line, said bit of information to a logic state rendering said one of said transistors non-conductive, further comprising a write line and pair of data input lines, and wherein each of said memory cells further comprises a transistor connected to a respective one of said data input lines and having a gate connected to said write line for setting said bit of information to a logic state specified by a data signal asserted on said respective one said data input lines when a write enable signal is asserted on said write line, further comprising a logic circuit connecting said pair of data input lines to a single data line of said data bus and to a mask bit line so that when a mask bit is asserted on said mask bit line and a write enable signal is asserted on said write enable line, data are written into said pair of memory cells representing said "don't care" state, and when a mask bit is not asserted on said mask bit line and a write enable signal is asserted on said write enable line, data are written into said pair of memory cells to represent another state that encodes a data bit on said single data line of said data bus.
Claim 9
Dependent Claim
83 words
The content addressable memory as claimed in claim 6 or 7, wherein each of said memory cells includes a pair of cross-coupled inverters for storing said bit of said information, one of said inverters having an output connected to the gate of said one of said transistors, and another of said inverters having an output connected to the gate of said another of said transistors, so that complementary logic levels are asserted on said gates of said transistors of said pair of transistors.
Claim 10
Independent Claim
209 words
A method of translating a virtual address to a physical address in a digital computer, said method comprising the steps of: a) storing a virtual page number in a tag store of a storage location of a content addressable memory, storing an associated physical page number in a data word of said storage location, and storing page granularity information as don't care states in said storage location, said don't care states specifying predetermined bits of said virtual page number in said tag store; b) matching a virtual page number specified by said virtual address to the virtual page number stored in said tag store of said storage location, and based on said don't care states in said storage location, detecting a match between each predetermined bit of said virtual page number stored in said tag store and a corresponding bit of said virtual page number specified by said virtual address, and upon detecting a match between each bit of said virtual page number specified by said virtual address and the virtual page number stored in said tag store of said storage location, retrieving said associated physical page number from said storage location; and c) determining said physical address from the associated physical page number retrieved from said storage location.
References Cited (Backward Citations)
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