Abstract The present invention relates to a semiconductor integrated circuit comprising: data storage means (18); pulse signal generating means (25) for detecting a change in address input and generating a pulse signal; and data detecting means (21) for detecting data stored in said data storage means (18) corresponding to the address input, the data detecting means (21) being connected to the pulse signal generating means (25) and controlled by said pulse signal from said pulse signal generating means (25). Pulse width detecting means (26) detect a width of said pulse signal generated by said pulse signal generating means (25), and generate a pulse signal when the width of said pulse signal outputted from said pulse signal generating means (25) is greater than a predetermined value. Data latching means (22; 27) latch the data detected by said data detecting means (21) when said pulse width detecting means (26) generates said pulse signal, and data output means (23) externally output the data latched by said data latching means (22; 27).
A semiconductor integrated circuit comprising: - data storage means (18); - pulse signal generating means (25) for detecting a change in address input and generating a pulse signal; and - data detecting means (21) for detecting data stored in said data storage means (18) corresponding to the address input, the data detecting means (21) being connected to the pulse signal generating means (25) and controlled by said pulse signal from said pulse signal generating means (25); characterized by further comprising: - pulse width detecting means (26) for detecting a width of said pulse signal generated by said pulse signal generating means (25), and for generating a pulse signal when the width of said pulse signal outputted from said pulse signal generating means (25) is greater than a predetermined value; - data latching means (22; 27) for latching the data detected by said data detecting means (21) when said pulse width detecting means (26) generates said pulse signal; and - data output means (23) for externally outputting the data latched by said data latching means (22; 27).
Claim 2
Dependent Claim
176 words
A semiconductor integrated circuit comprising: - data storage means (18); - pulse signal generating means (25) for detecting a change in address input and generating a pulse signal; and - data detecting means (21) for detecting data stored in said data storage means (18) corresponding to the address input, the data detecting means (21) being connected to the pulse signal generating means (25) and controlled by said pulse signal from said pulse signal generating means (25); characterized by further comprising: - pulse width detecting means (26) for detecting a width of said pulse signal generated by said pulse signal generating means (25), and for generating a pulse signal when the width of said pulse signal outputted from said pulse signal generating means (25) is greater than a predetermined value; - data latching means (22; 27) for latching the data detected by said data detecting means (21) when said pulse width detecting means (26) generates said pulse signal; and - data output means (23) for externally outputting the data latched by said data latching means (22; 27).