Patent EP0642133A2 successfully refreshed from Google Patents.
EP0642133A2
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EP
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Non-volatile memory device with a sense amplifier capable of copying back
Assignee: Toshiba Corp
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Filing: 1994-09-01
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Granted: —
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Expires: 2014-09-01
Abstract
Abstract Disclosed is a non-volatile semiconductor memory device for transferring data which is inverted data of held data onto bit lines, without reading out read data to an external unit, when data is copied back. This device comprises NAND memory cells (2) connected to bit lines (BL), a flip-flop circuit (1) for temporarily holding write data, a P channel transistor (Q1) for precharging the bit lines (BL) to a predetermined potential, an N channel transistor (Q2) for connecting the bit lines (BL) to the flip-flop circuit (1), and an N channel transistor (Q3) having both ends connected between a node (5) of the flip-flop circuit (1) on the opposite side to the bit lines (BL) and one end of the transistor (Q2) on the bit line side. The transistor (Q3) is provided to hold read data and then output a potential according to its inverted data onto the bit lines (BL). The individual terminals of the flip-flop circuit (1) are connected via a column gate (3) to an I/O line and a BI/O line (inverted-signal line of I/O).
Inventors
- 👤 Junichi C/O Intellectual Property Div. Miyamoto
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-06 19:48
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/34; G11C16/3418; G11C16/3431; G11C16/3436; G11C16/3454; G11C16/3459
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
126 words
A non-volatile semiconductor memory device comprising: memory cells (2) each constituted of a transistor having a charge accumulating layer, each for, in write mode, storing data corresponding to a threshold value which changes greatly as an absolute value of a difference between potentials applied to a drain and a gate becomes larger; bit lines (BL) to each of which drains of a plurality of memory cells are commonly connected; precharge means (Q1) for precharging said bit lines (BL) to a predetermined potential in read mode; data holding means (1, Q2) for temporarily holding data read from said memory cells; and inverted-data outputting means (Q3) for outputting a potential corresponding to inversion of said data held in said data holding means (1), to said bit lines (BL).
Claim 2
Dependent Claim
79 words
The non-volatile semiconductor memory device according to claim 1, characterized by further comprising verifying means (Q31, Q32) for verifying a writing operation on memory cells done by said inverted-data outputting means (Q3), said verifying means including transfer control means (Q3) for controlling connection between said bit lines (BL) to said data holding means (1), and there is a period for electrically disconnecting said bit lines (BL) from said data holding means (1) at a time of a verifying operation.
Claim 3
Dependent Claim
99 words
The non-volatile semiconductor memory device according to claim 2, characterized in that said verifying means includes a first verifying transistor (Q31) which conducts at a time of said verifying operation and a second verifying transistor (Q32) whose gate is controlled in accordance with a signal at a predetermined node (5) of said data holding means (1), whereby said first and second verifying transistors constitute a current path for controlling a potential of said bit lines (BL) in accordance with said signal at said predetermined node (5) of said data holding means (1) at a time of said verifying operation.
Claim 4
Dependent Claim
79 words
The non-volatile semiconductor memory device according to claim 2, characterized in that said verifying means includes a first verifying transistor (Q7) which conducts at a time of said verifying operation and a second verifying transistor (Q4) whose gate is controlled in accordance with a signal on said bit lines (BL), whereby said first and second verifying transistors constitute a current path for inverting data at a predetermined node (4) of said data holding means (1) when verification is completed.
Claim 5
Dependent Claim
97 words
A non-volatile semiconductor memory device according to claim 1, characterized in that said data holding means includes a bistable data holding circuit (1) having first and second latch nodes and a first transfer gate element (Q2) for controlling an interconnection of said bit lines to said first latch node (4) of said bistable data holding circuit (1), and said inverted-data outputting means includes said bistable data holding circuit (1) and a second transfer gate element (Q3) for controlling an interconnection of said bit lines to said second latch node (5) of said bistable data holding circuit (1).
Claim 6
Dependent Claim
57 words
The non-volatile semiconductor memory device according to claim 5, characterized in that in read mode, said bistable data holding circuit (1) is previously disabled, and is enabled after said bit lines (BL) and said precharge means (Q1) are set in a free running state to thereby hold data according to a potential of said bit lines then.
Claim 7
Dependent Claim
98 words
The non-volatile semiconductor memory device according to claim 6, characterized by further comprising a first verifying transistor (Q31) which conducts at a time of a verifying operation and a second verifying transistor (Q32) whose gate is controlled in accordance with a signal at said second latch node (5) of said bistable data holding circuit (1), whereby said first and second verifying transistors constitute a current path for controlling a potential of said bit lines (BL) in accordance with said signal at said other node (5) of said data holding circuit (1) at a time of said verifying operation.
Claim 8
Dependent Claim
194 words
The non-volatile semiconductor memory device according to claim 6, characterized by further comprising a first verifying transistor (Q21) which conducts at a time of a first verifying operation, a second verifying transistor (Q22) whose gate is controlled in accordance with a signal at said first latch node (4) of said bistable data holding circuit (1), a third verifying transistor (Q31) which conducts at a time of a second verifying operation, and a fourth verifying transistor (Q32) whose gate is controlled in accordance with a signal at said second latch node (5) of said bistable data holding circuit (1), whereby said first and second verifying transistors (Q21, Q22) constitute a first current path for controlling a potential of said bit lines (BL) in accordance with said signal at said first latch node (4) of said data holding circuit (1) at a time of said first verifying operation and said third and fourth verifying transistors (Q31, Q32) constitute a second current path for controlling a potential of said bit lines (BL) in accordance with said signal at said second latch node (5) of said data holding circuit (1) at a time of said second verifying operation.
Claim 9
Dependent Claim
65 words
The non-volatile semiconductor memory device according to claim 5, characterized in that in read mode, said bistable data holding circuit (1) is previously disabled, and data held in said bistable data holding circuit (1) is inverted or uninverted in accordance with a potential of said bit lines (BL) after said precharge means (Q1) and said bit lines (BL) are set in a free running state.
Claim 10
Dependent Claim
22 words
The non-volatile semiconductor memory device according to claim 9, characterized in that said bistable data holding circuit (1) has reset means (Q6).
Claim 11
Dependent Claim
73 words
The non-volatile semiconductor memory device according to claim 9, characterized by further comprising a first verifying transistor (Q5) which conducts at a time of said verifying operation and a second verifying transistor (Q4) whose gate is controlled in accordance with a signal on said bit lines (BL), whereby said first and second verifying transistors constitute a current path for inverting data in said data holding means (1) when said verifying operation is completed.
Claim 12
Dependent Claim
123 words
The non-volatile semiconductor memory device according to claim 9, characterized by further comprising a first verifying transistor (Q5) which conducts at a time of a first verifying operation, a second verifying transistor (Q7) which conducts at a time of a second verifying operation, and a third verifying transistor (Q4) whose gate is controlled in accordance with a signal on said bit lines (BL), whereby said first and third verifying transistors (Q5, Q4) constitute a first current path for inverting data in said data holding circuit (1) when said first verifying operation is completed and said second and third verifying transistors (Q7, Q4) constitute a second current path for inverting data in said data holding circuit (1) when said second verifying operation is completed.
Claim 13
Dependent Claim
52 words
The non-volatile semiconductor memory device according to claim 5, characterized in that said memory cells are provided in a matrix form and a structural unit of said bistable data holding circuit (1) and said first and second transfer gate elements (Q2, Q3) is commonly connected to a plurality of bit lines (BL).
Claim 14
Dependent Claim
139 words
The non-volatile semiconductor memory device according to claim 5 or 13, characterized in that said memory cells are provided in a matrix form and there are a plurality of structural units of said bistable data holding circuit (1) and said first and second transfer gate elements (Q2, Q3), each structural unit renders said first transfer gate element (Q2) conductive and said second transfer gate element (Q3) non-conductive in read mode to simultaneously sense a plurality of bit line potentials, and after data of said bistable data holding circuit (1) is entirely unchanged or only a part of said data is changed externally, said each structural unit renders said first transfer gate element (Q2) non-conductive and said second transfer gate element (Q3) conductive in write mode, thereby transferring contents of said data holding circuit (1) onto said bit lines (BL).
Claim 15
Dependent Claim
43 words
The non-volatile semiconductor memory device according to claim 14, characterized in that a first row (2-X) of memory cells in said matrix is selected in read mode, and a second row (2-1) of memory cells in said matrix is selected in write mode.
Claim 16
Dependent Claim
35 words
The non-volatile semiconductor memory device according to claim 15, characterized by further including means for previously erasing contents of said memory cells connected to said second row (2-1) before said second row (2-1) is selected.
References Cited (Backward Citations)
No citation records indexed.
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