Semiconductor integrated circuit device having signal wiring construction for suppressing clock skew

Abstract

Abstract In a semiconductor integrated circuit device (10), a clock signal wiring for transmitting a clock signal to flip-flops (6) is constituted from a plurality of trunk clock signal lines (1) connected to a clock driver (5) by way of equal length lines, and a plurality of clock signal branch lines (8) branching from the trunk clock signal lines. The flip-flops may be connected directly or indirectly via the clock signal branch lines (8) to the trunk clock signal lines (1). In this instance, one of a pair of terminal ends of each trunk clock signal line (1) is connected to the clock driver (5) while the other terminal end is set as an open end (2), and the transmission loss in the trunk clock signal line (1) is sufficiently small. Accordingly, as reflected waves of the input clock signal at both terminal ends are present in trunk clock signal line (1) and the voltage waveform in trunk clock signal line (1) presents a composite waveform of the incident wave and the reflected waves, the clock skew in the semiconductor integrated circuit device is suppressed to a very low level even where the semiconductor integrated circuit device is formed as a large scale integrated circuit.

Inventors

• 👤 Hitoshi Okamura
• 👤 Shin-Ichi Ohkawa

Bibliographic Details