Abstract In a semiconductor integrated circuit device (10), a clock signal wiring for transmitting a clock signal to flip-flops (6) is constituted from a plurality of trunk clock signal lines (1) connected to a clock driver (5) by way of equal length lines, and a plurality of clock signal branch lines (8) branching from the trunk clock signal lines. The flip-flops may be connected directly or indirectly via the clock signal branch lines (8) to the trunk clock signal lines (1). In this instance, one of a pair of terminal ends of each trunk clock signal line (1) is connected to the clock driver (5) while the other terminal end is set as an open end (2), and the transmission loss in the trunk clock signal line (1) is sufficiently small. Accordingly, as reflected waves of the input clock signal at both terminal ends are present in trunk clock signal line (1) and the voltage waveform in trunk clock signal line (1) presents a composite waveform of the incident wave and the reflected waves, the clock skew in the semiconductor integrated circuit device is suppressed to a very low level even where the semiconductor integrated circuit device is formed as a large scale integrated circuit.
Inventors
👤 Hitoshi Okamura
👤 Shin-Ichi Ohkawa
Bibliographic Details
Application Number—
JurisdictionEP
Data Sourcegoogle_patents
Last Synchronized2026-11-02 17:51
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/04; G06F1/10
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
169 words
A semiconductor integrated circuit device, comprising: a plurality of trunk clock signal lines formed in at least one wiring layer of a plurality of wiring layers on a semiconductor substrate; a plurality of clock signal branch lines connected to said trunk clock signal lines, formed in the same or other layer with said trunk clock signal lines and having a line width and a line film thickness smaller than those of said trunk clock signal line; a plurality of circuit elements each having a clock input terminal connecting directly to said trunk clock signal line or indirectly by way of said clock signal branch line to said trunk clock signal line; and one of a pair of terminals of each trunk clock signal line being connected to a clock driver by way of an equal length line while the other terminal of said trunk clock signal line is open-ended so that the signal reflection coefficient at the open-ended terminal of said trunk clock signal line is substantially sufficiently high.
Claim 2
Dependent Claim
30 words
A semiconductor integrated circuit device as claimed in claim 1, wherein said trunk clock signal lines or said clock signal branch lines are formed in two or more wiring layers.
Claim 3
Dependent Claim
30 words
A semiconductor integrated circuit device as claimed in claim 2, wherein said trunk clock signal lines are formed in the upper layer than that of said clock signal branch lines.
Claim 4
Dependent Claim
38 words
A circuit device as claimed in claim 1, 2 or 3, wherein said trunk clock signal line forms a wiring layer in the same layer as a bump metal layer to be used for tape automated bonding mounting.
Claim 5
Dependent Claim
64 words
A circuit device as claimed in any of claims 1 to 4, wherein an integral number of times a value obtained by dividing four times the length of said trunk clock signal line by the propagation speed of the clock voltage waveform which advances in said drunk clock signal line is substantially equal to the rising or falling time of the clock voltage waveform.
References Cited (Backward Citations)
No citation records indexed.
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