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EP0704852A2
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Novolatile semiconductor memory cell capable of saving overwritten cell and its saving method
Assignee: Toshiba Corp
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Filing: 1995-09-29
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Granted: —
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Expires: 2015-09-29
Abstract
Abstract If data is read from a selected memory cell (MC1 to MCn) at the time of overwrite verifying, a potential of a bit line is changed in accordance with data. If a transistor (Q1) is turned on, a latch circuit (LT) is set in accordance with data of the bit line (BL1). In a case where there is a memory cell being in an overwrite state, data of the selected memory cell is latched to the latch circuit (LT), and data corresponding to one page is erased. Thereafter, a normally writing operation is executed by data latch to the latch circuit (LT), thereby the memory cell being in the overwrite state can be used as a normal threshold voltage.
Inventors
- 👤 Keniti c/o Intellectual Prop. Div. Imamiya
- 👤 Hiroshi c/o Intellectual Prop. Div. Nakamura
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-27 05:55
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/34; G11C16/3404; G11C16/3413; G11C16/10; G11C16/14; G11C16/16
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
123 words
A nonvolatile semiconductor memory device characterized by comprising: a memory cell array (21-1) including a plurality of memory cells (MC1 to MCn): a bit line (BL1) to which said memory cell array (21-1) is connected: a latch circuit (LT) for latching data to be written to said memory cell and data read from said memory cell; and controllers (Q1 to Q4) connected between said latch circuit and said bit line, wherein when a memory cell being in an overwrite state is present in said plurality of memory cells, said controllers read data of the memory cell to be copied to said latch circuit, data of said memory cell is erased, thereafter data copied to said latch circuit is written to said memory cell.
Claim 2
Dependent Claim
45 words
A device according to claim 1, characterized in that said memory cell array (21-1) constitutes an NAND-structured memory cell having current paths of said plurality of memory cells connected in series, and one end of the NAND-structured memory cell is connected to said bit line.
Claim 3
Dependent Claim
34 words
A device according to claim 1, characterized in that said memory cell (MC1 to MCn) selectively increase a threshold voltage at the time of writing data, and decrease the threshold voltage in the lump.
Claim 4
Dependent Claim
52 words
A device according to claim 1, characterized in that the current paths of said plurality of memory cells (MC1 to MCn) are connected to the bit line in parallel, and said memory cells selectively decrease the threshold voltage at the time of writing data, and increase the threshold voltage in the lump.
Claim 5
Dependent Claim
22 words
A device according to claim 4, characterized in that said plurality of memory cells (MC1 to MCn) comprises a NOR-structured memory cell.
Claim 6
Dependent Claim
23 words
A device according to claim 4, characterized in that said plurality of memory cells (MC1 to MCn) comprises an AND-structured memory cell (190).
Claim 7
Dependent Claim
23 words
A device according to claim 4, characterized in that said plurality of memory cells (MC1 to MCn) comprises a DINOR-structured memory cell (191).
Claim 8
Dependent Claim
19 words
A device according to claim 1, characterized in that said erasing means (17) erases data corresponding to one page.
Claim 9
Dependent Claim
43 words
A device according to claim 1, characterized in that said erasing means (17) erases data corresponding to one page, and said erasing means (17) sets the threshold voltage of the overwrite memory cell to the threshold voltage of the normally written memory cell.
Claim 10
Dependent Claim
28 words
A device according to claim 1, characterized in that said latch circuit (LT) has first and second nodes (A, B) and stores write data to the first node.
Claim 11
Dependent Claim
256 words
A device according to claim 10, characterized in that said controllers includes: a first transistor (Q4) having one end of the current path connected to said first node (A) of said latch circuit (LT), and the other end connected to said bit line (BL1), wherein said first transistor supplies data stored in said first node to a selected memory cell of said memory cell array in accordance with a first timing signal (φ4) supplied to a gate; a second transistor (Q3) having a gate connected to said bit line (BL1), wherein a conductive state of said second transistor is controlled in accordance with a potential of said bit line; a third transistor (Q2) having one of the current path connected to said second node (B) of said latch circuit (LT) and the other end of the current path connected to one of said current path of said second transistor, wherein said third transistor transmits a potential of said bit line to said second node in accordance with a second timing signal (φ2) supplied to the gate at the time of write verifying; and a fourth transistor (Q1) having one of the current path connected to said first node (A) and the other end of the current path connected to one of said current path of said second transistor (Q3), wherein said fourth transistor (Q1) transmits a potential of said bit line to said first node in accordance with a third timing signal (φ1) supplied to the gate at the time of overwrite verifying and reading data.
Claim 12
Dependent Claim
23 words
A device according to claim 11, characterized in that said first to fourth transistors (Q4, Q3, Q2, Q1) comprise an N channel transistor.
Claim 13
Dependent Claim
32 words
A device according to claim 11, characterized in that said first transistor (Q4) comprises an N channel transistor, and said second to fourth transistors (Q3, Q2, Q1) comprise a P channel transistor.
Claim 14
Independent Claim
58 words
A method for saving overwrite of a nonvolatile semiconductor memory device characterized by comprising the steps of: reading data of a memory cell to be copied to a latch circuit when data is overwritten to the memory cell (ST4); erasing data of said memory cell (ST5); writing data copied to said latch circuit to said memory cell (ST1).
Claim 15
Dependent Claim
42 words
A method according to claim 14, characterized by further comprising: a write verifying step (ST2) of reading written data by supplying a first voltage to a gate of a selected memory cell to verify whether or not said read data is normal.
Claim 16
Dependent Claim
60 words
A method according to claim 14, characterized by further comprising: an overwrite verifying step (ST3) of reading data from the memory cell by supplying a second voltage different from said first voltage to the gate of said memory cell to verify whether or not said read data is normal when a verify result is normal in said write verifying step.
Claim 17
Dependent Claim
30 words
A method according to claim 14, characterized by further comprising said erasing step (ST5) erases data of the plurality of memory cells connected to one word line in the lump.
Claim 18
Dependent Claim
92 words
A method according to claim 14, characterized by further comprising the steps of: reading data of a memory cell to be copied to a latch circuit (LT) when data is overwritten to the memory cell (ST4); erasing data of said memory cell such that a threshold voltage of an overwrite memory cell is set to a threshold voltage of a normally written memory cell (ST6); and reading data by supplying a first voltage to a gate of a selected memory cell to verify whether or not said read data is normal (ST2).
References Cited (Backward Citations)
No citation records indexed.
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