Patent EP0705050A2 successfully refreshed from Google Patents.
EP0705050A2
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Communication LSI
Assignee: Toshiba Corp
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Filing: 1995-09-29
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Granted: —
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Expires: 2015-09-29
Abstract
Abstract A communication LSI comprises a reception frame disassembling section 1 for receiving data from a network, a reception cell processing section 2 for processing a payload portion of the data disassembled in the reception frame disassembling section and outputting a result thereof to an ATM layer, a reception overhead memory 3 for storing an overhead portion of the data disassembled in the reception frame disassembling section, a receiving processor 4 for executing processes in the overhead portion by inputting desired data stored in the reception overhead memory when data is received, a status register 5 for storing a result processed in the receiving processor, a transmitting processor 6 for executing processes in the overhead portion by inputting the result stored in the status register when data is transmitted, a transmission overhead memory 7 for storing an output of the transmitting processor, a transmission cell processing section 8 for receiving data from an ATM layer, and a transmission frame assembling section 9 for assembling an output of the transmission cell processing section and an output of said transmission overhead memory in a frame and transmitting the frame to a network.
Inventors
- 👤 Yuichi Miyazawa
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-30 13:47
CPC Classifications
H; H04; H04L; H04L12/00; H04L12/28; H04L12/42; H04L12/427; H04L12/43; H04Q; H04Q11/00; H04Q11/04; H04Q11/0428; H04Q11/0478; H04J; H04J3/00; H04J3/02; H04J3/14; H04J3/16; H04J3/1605; H04J3/1611; H04J3/1617; H04J2203/00; H04J2203/0001; H04J2203/0089; H04L12/54; H04L12/56; H04L12/5601; H04L2012/5672; H04L7/00; H04L7/04; H04L7/048
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
31 words
A communication LSI for executing protocol processes of a physical layer in B-ISDN, comprising: a memory for storing overhead information; and a processor for executing a program for said protocol processes.
Claim 2
Dependent Claim
39 words
A communication LSI according to claim 1, wherein said processor is changed from a standby state to an active state of predetermined operation in response to an input of a signal in synchronization with frames of said physical layer.
Claim 3
Dependent Claim
53 words
A communication LSI according to claim 1, wherein said signal in synchronization with said frames of said physical layer is generated in correspondence to each row of said frames of said physical layer, and said program for said protocol processes is defined correspondingly to each row of said frames of said physical layer.
Claim 4
Dependent Claim
45 words
A communication LSI according to claim 1, wherein said processor comprises: a receiving processor for executing said program for said protocol processes when a receiving operation is executed; and a transmitting processor for executing said program for protocol processes when a transmitting operation is executed.
Claim 5
Dependent Claim
199 words
A communication LSI executing protocol processes of a physical layer in B-ISDN, comprising; a reception frame disassembling section for receiving data from a network; a reception cell processing section for processing a payload portion of said data disassembled in said reception frame disassembling section, and outputting a result thereof to an ATM layer; a reception overhead memory section for storing an overhead portion of said data disassembled in said reception frame disassembling section; a receiving processor section for executing processes in said overhead portion by inputting desired data stored in said receiving overhead memory section when data is received; a status register section for storing a result processed in said receiving processor section; a transmitting processor section for executing processes in said overhead portion by inputting said result stored in said status register section when data is transmitted; a transmission overhead memory section for storing an output of said transmitting processor section; a transmission cell processing section for receiving data from an ATM layer; and a transmission frame assembling section for assembling an output of said transmission cell processing section and an output of said transmission overhead memory section in a frame, and transmitting said frame to said network.
Claim 6
Dependent Claim
120 words
A communication LSI according to claim 5, wherein said receiving processor section comprises: a program counter for holding an address in which an instruction to be executed succeedingly to an instruction which is being executed presently is stored; a memory for outputting said instruction stored in said address which is held by said program counter; an instruction register for holding said instruction output from said memory; an instruction decoder for decoding said instruction held by said instruction register; a selector for selecting data from said reception frame disassembling section and said reception overhead memory section; a register for holding data selected by said selector; and an arithmetic section for inputting said data held by said register and processing said data.
Claim 7
Dependent Claim
27 words
A communication LSI according to claim 5, wherein said reception overhead memory section stores SOH, AU pointer, and POH in said overhead portion as their structures remain.
Claim 8
Dependent Claim
25 words
A communication LSI according to claim 6, wherein said memory comprises a RAM capable of storing said program for said protocol processes and modifying them.
Claim 9
Dependent Claim
13 words
A communication LSI according to claim 6, wherein said memory comprises a ROM.
Claim 10
Dependent Claim
120 words
A communication LSI according to claim 5, wherein said transmitting processor section comprises: a program counter for holding an address in which an instruction to be executed succeedingly to an instruction which is being executed presently is stored; a memory for outputting said instruction stored in said address which is held by said program counter; an instruction register for holding said instruction output from said memory; an instruction decoder for decoding said instruction held by said instruction register; a selector for selecting data from said reception frame disassembling section and said reception overhead memory section; a register for holding data selected by said selector; and an arithmetic section for inputting said data held by said register and processing said data.
Claim 11
Dependent Claim
25 words
A communication LSI according to claim 10, wherein said memory comprises a RAM capable of storing said program for said protocol processes and modifying them.
Claim 12
Dependent Claim
13 words
A communication LSI according to claim 10, wherein said memory comprises a ROM.
References Cited (Backward Citations)
No citation records indexed.
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