Apparatus to control load/store instructions

Claim 2

The pipelined processor according to claim 1 wherein said control means comprises a rename unit controlling dispatch of instructions, issuing instructions to execution units, and writeback of instructions, said rename unit performing source operand dependency analysis, providing instruction scheduling wherein oldest instructions are executed first, enabling any execution or memory access instruction to execute out-of-order, and rapid pipeline recovery due to a mispredicted branch or a store load conflict, the store barrier cache being accessed by the rename unit as instructions are fetched from an instruction cache.

Claim 3

The pipelined processor according to claim 2 wherein the store barrier cache contains history bits that are used to predict a store load conflict, the rename unit marking a store instruction during a dispatch pipeline stage so that no loads in program order are permitted to execute ahead of the store that is predicted to be violated.

Claim 4

A pipelined processor capable of dispatching, issuing and executing multiple instructions in a single processor cycle comprising: a plurality of function units, including a load/store function unit, for executing pipelined instructions; an instruction cache for storing instructions to be executed by said function units; an instruction fetch and dispatch unit connected to said instruction cache for accessing said instructions and dispatching the instructions to the function units for execution; a data cache for storing data to be operated on by said function units when executing said instructions, said data cache being connected to said load/store function unit to supply data to said function units for the execution of said instructions; a completion buffer connected to said function units for storing results from the execution of said instructions; a rename unit connected to said instruction fetch and dispatch unit for maintaining a stack order of most recently dispatched to least recently dispatched instruction and controlling the dispatch of instructions in order; and apparatus to dynamically control the out-of-order execution of load/store instructions in the processor, said apparatus including a store barrier cache storing data used to predict whether or not a store violation is likely to occur and, if so, said apparatus setting a control bit in the rename unit to indicate that a store violation condition has been predicted so as to restrict the issue of instructions to the load/store function unit to program order until the store instruction has been executed and it is once again safe to proceed with out-of-order execution.

Claim 5

The pipelined processor recited in claim 4 wherein said store barrier cache stores history bits for virtual addresses to record a state of a persistence condition for each cache store barrier entry.

Claim 7

The method according to claim 6 further comprising the steps of: storing history bits in the store barrier cache to predict a store load conflict; and marking a store instruction during a dispatch pipeline stage so that no loads in program order are permitted to execute ahead of the store that is predicted to be violated.