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EP0735482A1
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A parallelized master request class structure for interfacing a processor in a packet switched cache coherent multiprocessor system
Assignee: Sun Microsystems Inc
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Filing: 1996-03-21
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Granted: —
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Expires: 2016-03-21
Abstract
Abstract A multiprocessor computer system is provided having a multiplicity of sub-systems and a main memory coupled to a system controller. An interconnect module, interconnects the main memory and sub-systems in accordance with interconnect control signals received from the system controller. At least two of the sub-systems are data processors, each having a respective cache memory that stores multiple blocks of data and a respective master cache index. Each master cache index has a set of master cache tags (Etags), including one cache tag for each data block stored by the cache memory. Each data processor includes a master interface for sending memory transaction requests to the system controller and for receiving cache access requests from the system controller corresponding to memory transaction requests by other ones of the data processors. In the preferred embodiment, each memory transaction request is classified into one of two distinct master classes: a first transaction class including read memory access requests and a second transaction class including writeback memory access requests. The master interface and system controller have corresponding parallel request queues, one for each master class, for transmitting and receiving memory access requests. The system controller further includes memory transaction request logic for processing each memory transaction request and a duplicate cache index having a set of duplicate cache tags (Dtags), including one cache tag corresponding to each master cache tag in an associated data processor.
Inventors
- 👤 William C. Van Loo
- 👤 Zahir Ebrahim
- 👤 Satyanarayana Nishtala
- 👤 Kevin Normoyle
- 👤 Leslie Kohn
- 👤 Louis F. Coffin Iii
- 👤 Charles E. Narad
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-29 22:26
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0806; G06F12/0815; G06F12/0817; G06F12/0828
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
269 words
A computer system, comprising: a system controller; a main memory coupled to said system controller; a data processor having a cache memory having cache lines for storing data blocks, a master cache index having master cache tags (Etags) including one Etag for each said cache line in said cache memory, and a writeback buffer for storing a dirty victim data block displaced from said cache memory until it is written back into said main memory; said Etag for each cache line storing an address index and an Etag state value that indicates whether said data block stored in said cache line includes data modified by said data processor; said data processor including a master interface, coupled to said system controller, for sending memory transaction requests to said system controller, said master interface including at least two parallel independent outbound request queues for storing memory transaction requests to be sent to said system controller; said memory transaction requests including a first transaction class that includes read memory transaction requests and a second transaction class that includes writeback memory transaction requests, wherein memory transaction requests in said first transaction class are stored by said data processor in a first one of said outbound request queues and memory transaction requests in said second transaction class are stored by said data processor in a second one of said outbound request queues; said system controller including a corresponding interface coupled to said data processor for receiving memory transaction requests from said data processor, said interface including at least two parallel independent incoming request queues for storing memory transaction requests received from said data processor.
Claim 2
Dependent Claim
144 words
The computer system of claim 1, said system controller including execution logic for executing said received memory transaction requests, including logic for executing said transactions in each of said outbound request queues in the same order that said transactions were stored by said data processor in said each outbound request queue; wherein said system controller processes the memory transaction requests stored in said outbound request queues in accordance with resource availability such that a first of said memory transaction requests stored in one of said outbound request queues may be processed later by said system controller than a second of said memory transaction requests stored in a second of said outbound request queues even when said second memory transaction request is stored in said second outbound request queue later than when said first memory transaction request is stored in said first outbound request queue.
Claim 3
Dependent Claim
157 words
A computer system, comprising: a system controller; a main memory coupled to said system controller; a data processor having a cache memory having cache lines for storing data blocks; said data processor having a master interface, coupled to said system controller, for sending memory transaction requests to said system controller, said master interface including at least two parallel independent outbound request queues for storing memory transaction requests to be sent to said system controller; said memory transaction requests defining at least two transaction classes corresponding to said at least two outbound request queues, including a first transaction class that includes read memory transaction requests and a second transaction class that includes writeback memory transaction requests; said system controller including a corresponding interface coupled to said data processor for receiving memory transaction requests from said data processor, said interface Including at least two parallel independent incoming request queues for storing memory transaction requests received from said data processor.
Claim 4
Dependent Claim
79 words
The computer system of claim 3 further including independent outbound data queues in said data processor, one for each of said transaction classes, said outbound data queues filled by said data processor prior to the transmission of an associated memory transaction request to said system controller, said outbound data queues storing data blocks associated with said memory transaction requests; said system controller including memory transaction request logic for processing each of said memory transaction requests by said data processor.
Claim 5
Dependent Claim
107 words
The computer system of claim 4 wherein each of said two parallel independent outbound request queues in said data processor is a first-in-first-out buffer for transmitting memory transaction requests to the system controller, said memory transaction request logic, responsive to each of said received transaction requests, generating a reply for transmission to said data processor upon the availability of resources associated with said memory transaction request, said replies strictly ordered in each transaction class such that said data processor receives replies to those of said memory transaction requests transmitted from a transaction class in the same order as the transactions were originally issued from said data processor.
Claim 6
Dependent Claim
103 words
The computer system of any claims 3 to 5 further including: said data processor including a slave interface, coupled to said system controller, for receiving transaction requests from said system controller, said slave interface including at least one input request queue for storing transaction requests received from said system controller; said transaction requests including read requests and write requests; each said transaction request specifying an address for an associated data block to be read or written; said system controller having a second interface including at least one outbound request queue for storing transaction requests to be transmitted to said data processor's slave interface.
Claim 7
Dependent Claim
139 words
The computer system of any claims 3 to 6, said system controller including transaction execution logic for executing said transactions in each of said outbound request queues in the same order that said transactions were stored by said data processor in said each outbound request queue; wherein said system controller processes the memory transaction requests stored in said outbound request queues in accordance with resource availability such that a first of said memory transaction requests stored in one of said outbound request queues may be processed later by said system controller than a second of said memory transaction requests stored in a second of said outbound request queues even when said second memory transaction request is stored in said second outbound request queue later than when said first memory transaction request is stored in said first outbound request queue.
Claim 8
Dependent Claim
386 words
A computer system, comprising: a system controller; a main memory coupled to said system controller; a plurality of data processors each having a cache memory having cache lines for storing data blocks; each said data processor having a master interface, coupled to said system controller, for sending memory transaction requests to said system controller, said master interface including at least two parallel independent outbound request queues for storing memory transaction requests to be sent to said system controller; said memory transaction requests defining at least two transaction classes corresponding to said at least two outbound request queues, including a first transaction class that includes read memory transaction requests and a second transaction class that includes writeback memory transaction requests; said system controller including an interface coupled to each said data processor for sending and receiving memory transaction requests to and from each said data processor, said interface including at least two parallel independent incoming request queues for each data processor for storing memory transaction requests received from each said data processor; each said data processor including a slave interface, coupled to said system controller, for receiving transaction requests from said system controller, said slave interface including at least one input request queue for storing transaction requests received from said system controller; said transaction requests including read requests and write requests; each said transaction request specifying an address for an associated data block to be read or written; said system controller having a second interface for each said data processor including at least one output request queue for storing transaction requests to be transmitted to each said data processor's slave interface, wherein each said transaction request to be transmitted corresponds to one of said memory transaction requests received by said system controller from a requesting one of said data processors and has an associated transaction class; each said slave interface including logic for responding to received transactions requests by generating a reply for transmission to said system controller upon the availability of resources associated with said transaction requests, said replies strictly ordered for each transaction class in said requesting data processors such that said slave interface replies to transaction requests in the same order as the corresponding memory transaction requests were originally stored in their respective outbound request queues by said requesting one of said data processors.
Claim 9
Dependent Claim
136 words
The computer system of claim 8, said system controller including transaction execution logic for executing said transactions in each of said outbound request queues in the same order that said transactions were stored by said data processor in said each outbound request queue; wherein said system controller processes the memory transaction requests stored in said outbound request queues in accordance with resource availability such that a first of said memory transaction requests stored in one of said outbound request queues may be processed later by said system controller than a second of said memory transaction requests stored in a second of said outbound request queues even when said second memory transaction request is stored in said second outbound request queue later than when said first memory transaction request is stored in said first outbound request queue.
Claim 10
Independent Claim
166 words
A method for parallelizing memory transactions in a packet switched cache coherent multiprocessor system having a system controller coupled to a main memory and to a data processor having a cache memory comprising the steps of: sending memory transaction requests from said data processor to said system controller, including storing said memory transaction requests in at least two parallel independent outbound request queues; said memory transaction requests defining at least two transaction classes corresponding to said at least two outbound request queues, including a first transaction class that includes read memory transaction requests and a second transaction class that includes writeback memory transaction requests; receiving said memory transaction requests at said system controller and storing said received memory transaction requests in at least two parallel independent incoming request queues, such that said memory transaction requests for each of said transaction classes are stored in distinct ones of incoming request queues; and processing, at said system controller, each of said memory transaction requests by said data processor.
Claim 11
Dependent Claim
43 words
The method of claim 10 further including: for write transaction requests, storing data in independent outbound data queues in said data processor, one for each of said transaction classes, prior to the transmission of the associated write transaction request to said system controller.
Claim 12
Dependent Claim
89 words
The method of claim 10 or claim 11, wherein said processing step includes: in response to each of said received transaction requests, generating a reply for transmission to said data processor upon the availability of resources associated with said memory transaction request, said replies strictly ordered with respect to memory transaction requests in each transaction class such that said data processor receives replies to those of said memory transaction requests transmitted from a transaction class in the same order as the transactions were originally issued from said data processor.
Claim 13
Independent Claim
79 words
The method of any of claims 10 to 12 further including: receiving at said data processor transaction requests from said system controller corresponding to said memory transaction requests received by said system controller, said transaction requests including read requests and write requests; each said transaction request specifying an address for an associated data block to be read or written; said system controller storing in at least one outbound request queue transaction requests to be transmitted to said data processor.
Claim 14
Independent Claim
124 words
The method of any cf claims 10 to 13, said processing step including: processing said transactions in each of said outbound request queues in the same order that said transactions were stored in said each outbound request queue; and processing the memory transaction requests stored in said outbound request queues in accordance with resource availability such that a first of said memory transaction requests stored in one of said outbound request queues may be processed later than a second of said memory transaction requests stored in a second of said outbound request queues even when said second memory transaction request is stored in said second outbound request queue later than when said first memory transaction request is stored in said first outbound request queue.
References Cited (Backward Citations)
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