Patent EP0748124A2 successfully refreshed from Google Patents.
EP0748124A2
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Signal processing apparatus and method
Assignee: Discovision Associates
•
Filing: 1996-03-19
•
Granted: —
•
Expires: 2016-03-19
Abstract
Abstract An integrated digital communication system utilizing multilevel vestigial sideband transmission is provided. The communication system receives a multi-level pulse-amplitude modulated digital signal from a limited bandwidth channel. The system includes processing stages which demodulate, sample and filter the incoming signal prior to recovery of the digital data. Other stages recover the timing and lock on to the frequency and phase of the transmitted signal, as well as provide for automatic gain control. An adaptive equalizer, error correction circuitry, and an output interface recover the digital data and provide for transfer to other devices.
Inventors
- 👤 Anthony P.J. Claydon
- 👤 Charles D. Macfarlane
- 👤 Richard J. Gammack
- 👤 Anthony M. Jones
- 👤 William P. Robbins
- 👤 Mark Barnes
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-28 14:24
CPC Classifications
H; H04; H04L; H04L1/00; H04L1/004; H04L1/0056; H04L1/0057; H03; H03K; H03K5/00; H03K5/22; H03K5/24; H03M; H03M13/00; H03M13/03; H03M13/05; H03M13/13; H03M13/15; H03M13/151; H03M13/27; H03M13/2703; H03M13/2707; H03M13/276; H03M13/2764; H04L1/0045; H04L1/0071; H04L25/00; H04L25/02; H04L25/03; H04L25/03006; H04L25/03012; H04L25/03019; H04L25/03038; H04L25/03828; H04L25/03866; H04L25/06; H04L25/061; H04L25/062; H04L27/00; H04L27/02; H04L27/18; H04L27/22; H04L27/227; H04L27/2271; H04L27/2273; H04L27/32; H04L27/34; H04L27/38; H04L27/3809; H04N; H04N21/00; H04N21/40; H04N21/41; H04N21/426; H04N5/00; H04N5/14; H04N5/21; H04N5/211; H04N5/44; H04N5/4446; H04N5/455; H04N5/52; H04L27/0014; H04L2027/0024; H04L2027/0026; H04L2027/0032; H04L2027/0044; H04L2027/0053; H04L2027/0061; H04L2027/0063; H04L2027/0067; H04L2027/0071; H04L2027/0073; H04L2027/0079; H04L2027/0081; H04L7/00; H04L7/02; H04L7/033; H04L7/0334
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
151 words
A signal processing apparatus for the reception of data packets that are transmitted through a channel as a modulated signal having pretransmission characteristics, the signal processing apparatus comprising: an analog-to-digital converter that samples an input signal at sampling intervals and has an ADC output; a timing recovery circuit coupled to said ADC output, for adjusting a frequency and a phase of said sampling intervals; a carrier recovery circuit coupled to said ADC output, for adjusting a frequency and a phase of said input signal; a filter for conforming a characteristic of said ADC output to a pretransmission characteristic of said input signal; an adaptive equalizer coupled to said filter; an error correcting circuit coupled to said equalizer; and an output interface, coupled to said error correcting circuit; wherein said timing recovery circuit, said carrier recovery circuit, said equalizer, said error correcting circuit, and said output interface comprise a semiconductor integrated circuit.
Claim 2
Dependent Claim
42 words
The apparatus according to claim 1 wherein said modulated signal is modulated by vestigial sideband modulation, further comprising: an amplifier coupled to said channel and accepting said modulated signal therefrom; and a demodulator coupled to said amplifier for producing a demodulated signal.
Claim 3
Dependent Claim
36 words
The apparatus according to claim 1 or claim 2, wherein a plurality of said data packets are grouped in frames, each said frame further comprising a frame header, and a training sequence in said frame header.
Claim 4
Independent Claim
53 words
The apparatus according to claims 1 through 3, wherein said equalizer comprises: a first response filter; and a circuit for adjusting coefficients of said first response filter, said circuit being responsive to an error signal that is derived from a difference between an output of said first response filter and said training sequence.
Claim 5
Independent Claim
22 words
The apparatus according to claims 1 through 4, wherein said circuit for adjusting said coefficients comprises means for executing a least-mean-square algorithm.
Claim 6
Independent Claim
140 words
The apparatus according to claims 1 - 5, wherein said equalizer further scomprises: a phase tracking circuit for producing an in-phase component and a quadrature component that is representative of said modulated signal in accordance with - the formula data = a ( t )cosφ+ â ( t )sinφ wherein data is an output φ is phase error; a(t) is transmitted data; â(t) is the quadrature component of a(t); wherein an output of said phase tracking circuit is in accordance with the formula output c = a(t) (cosθ cosφ + sinθ sinφ) + â(t) (sinφ cosθ - cosφsinθ) wherein θ is an angle of rotation of a signal constellation of said modulated signal, said phase tracking circuit comprising; a second response filter; and circuit means including said second response filter for estimating said angle θ according to said least-mean-square algorithm.
Claim 7
Independent Claim
164 words
The apparatus according to claims 1 - 6, wherein blocks of said packets are interleaved at an interleaving depth, the apparatus further comprising a deinterleaving circuit that is incorporated in said integrated circuit, the deinterleaving circuit comprising: a random access memory for memorizing said interleaved packets, said random access memory having a capacity that does not exceed a block of interleaved data, and having a plurality of rows and a plurality of columns, wherein said rows define a plurality of groups; a first circuit for generating an address signal representing a sequence of addresses of said random access memory, wherein successive addresses differ by a stride; a second circuit for successively reading and writing data out of and into said random access memory respectively at an address of said random access memory that is determined by said address signal; and a third circuit for increasing said stride by said interleaving depth, wherein said stride is increased upon deinterleaving of a block of interleaved data.
Claim 8
Independent Claim
18 words
The apparatus according to claims 1 - 7 wherein said analog-to-digital converter is integrated in said integrated circuit.
Claim 9
Independent Claim
166 words
The apparatus according to claims 1 - 8, wherein said analog-to-digital converter comprises a comparator having first and second units, each of said units comprising: a capacitor connected to a first node and a second node; first switch means for connecting said first node to a selected one of an input voltage and a reference voltage; an inverter connected to said second node and having an output, wherein said inverter has a small-signal gain between said second node and said output thereof; and second switch means for connecting said output of said inverter of one of said first and second units to said first node of another of said first and second units, whereby said first and second units are cross-coupled in a positive feed back loop when said second switch means of said first unit and said second switch means of said second units are closed, and said output of said inverter is representative of a comparison of said input voltage and said reference voltage.
Claim 10
Independent Claim
33 words
The apparatus according to claims 1 - 9, wherein said filter further comprises a filter for downconverting said input signal to complex baseband representation and performing a Nyquist operation on said input signal.
Claim 11
Independent Claim
72 words
The apparatus according to claims 1 - 10, wherein said error correcting circuit comprises a Reed-Solomon decoder including a circuit for executing a Berlekamp algorithm, comprising: a first register for holding a portion of a locator polynomial Λ(x); a second register for holding a portion of a D polynomial; a first switch means for alternately selecting one of said first register and said second register in successive iterations of said Berlekamp algorithm.
Claim 12
Independent Claim
64 words
The apparatus according to claims 1 - 11, wherein said circuit for executing a Berlekamp algorithm further comprises a third register for holding a portion of an evaluator polynomial Ω(x); a fourth register for holding a portion of an A polynomial; a second switch means for alternately selecting one of said third register and said fourth register in successive iterations of said Berlekamp algorithm.
Claim 13
Independent Claim
192 words
The apparatus according to claims 1 - 12, wherein said output interface comprises a circuit for transferring data from a data source operating at a first clock rate provided by a first clock signal to a data sink operating at a second clock rate provided by a second clock signal comprising: first latch operable at said first clock rate; second latch operable at said second clock rate, said second latch receiving data from said first latch; first signal generator operable at said first clock rate; said first signal generator producing a data valid signal; at least one third latch operable at said second clock rate, said third latch receiving said data valid signal from said first signal generator in response to said second clock signal; second signal generator operable at said second clock rate, said second signal generator activating a load data signal to said second latch in response to receipt of said data valid signal from said third latch; whereby data is transferred from said first latch to said second latch in response to receipt by said second latch of said second clock signal when said load data signal is active.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.