Semiconductor memory

Claim 2

The semiconductor memory according to claim 1, characterized in that each of said banks has a bank-selecting circuit at the second end of every row of memory cells, and said bank-selecting circuit connects one of said banks to said data bus and disconnects the remaining banks from said data bus, in order to output and receive the multi-bit data.

Claim 3

The semiconductor memory according to claim 1, characterized in that said plurality of banks are four banks which are arranged in two rows and two columns.

Claim 4

The semiconductor memory according to claim 1, characterized by further comprising DQ-line pairs located among said sub-blocks, extending parallel to the rows of memory cells, and connecting said sense amplifiers to said DQ buffers

Claim 5

The semiconductor memory according to claim 1, characterized by further comprising column-selecting switches located among said sub-blocks and connected to said column-selecting lines.

Claim 6

The semiconductor memory according to claim 1, characterized in that said data input/output region is located at the first end of every column of memory cells.

Claim 7

The semiconductor memory according to claim 1, characterized in that said data input/output region has a plurality of data input/output circuits for receiving and outputting bits of the multi-bit data at the same time.

Claim 8

The semiconductor memory according to claim 1, characterized in that said data bus is provided on a center part of said memory chip and extending parallel to the columns of memory cells, and some of said banks are located on a first side of said data bus and the remaining banks are located on a second side of said data bus.

Claim 9

The semiconductor memory according to claim 1, characterized in that each of said banks has a plurality of column decoders, and every two adjacent of said column-selecting lines are controlled by one column decoder.

Claim 10

The semiconductor memory according to claim 1, characterized in that each of said row decoders selects one of the two sub-blocks and then one of the word lines extending over the sub-block selected.

Claim 11

A semiconductor memory according comprising: A. a memory chip (10); B. a plurality of main banks (11-0 to 11-3) arranged on said memory chip, for storing and outputting multi-bit data, independently of one another, each composed of a plurality of sub-banks (11-0-#0, 11-0-#1, to 11-3-#0, 11-3-#1), each of which comprises: a. a plurality of memory-cell blocks (BLa, BLb, BLc, BLd), each comprising two sub-blocks (CAL, CAR), sense amplifiers (SA), word lines (17), data lines (14) and column-selecting lines (15-0 to 15-3), each of said sub-blocks composed of one memory cell array, said sense amplifiers located between said two sub-blocks, said word lines, data lines and column-selecting lines arranged on the memory cell arrays constituting said two sub-blocks, said memory-cell blocks spaced apart along columns of memory cells and the column-selecting lines and data lines, and said sub-blocks spaced apart also along the columns of memory cells; b. at least one column decoder (CD0 to CD3) located at at least a first end of every column of memory cells and connected to said column-selecting lines; c. a plurality of row decoders (RD) located at a first end of every row of memory cells along which said word line extend, and connected to said word lines, each of said row decoders provided for one memory-cell block; d. a plurality of DQ buffers (DQ) located at a second end of every row of memory cells, each of said DQ buffers provided for one memory-cell block; e. a cell-array controller (CAC) located at a second end of very row of memory cells, for controlling the reading and writing of the multi-bit data; C. a data input/output region (12) provided on said memory chip, for receiving multi-bit data from an external device and outputting multi-bit data to an external device; and D. a plurality of data buses (B) provided for at least two of said sub-banks, extending parallel to the columns of memory cells, for transferring multi-bit data between said sub-banks, one the one hand, and said data input/output region, on the other.

Claim 12

The semiconductor memory according to claim 11, characterized in that each of said sub-banks has a bank-selecting circuit at the second end of every row of memory cells, and said bank-selecting circuit connects one of said banks to said data buses and disconnects the remaining banks from said data buses, in order to output and receive the multi-bit data.

Claim 13

The semiconductor memory according to claim 12, characterized in that data items are transferred through difference data buses, between the sub-banks selected, one the one hand, and said data input/output region, on the other.

Claim 14

The semiconductor memory according to claim 11, characterized by further comprising DQ-line pairs located among said sub-blocks, extending parallel to the rows of memory cells, and connecting said sense amplifiers to said DQ buffers.

Claim 15

The semiconductor memory according to claim 11, characterized by further comprising column-selecting switches located among said sub-blocks and connected to said column-selecting lines.

Claim 16

The semiconductor memory according to claim 11, characterized in that each of said main banks is composed of an n number of sub-banks, and said data input/output region has a plurality of data input/output circuits for receiving and outputting n times the bits of said multi-bit data, at the same time.

Claim 17

The semiconductor memory according to claim 11, characterized in that each of said sub-banks has a plurality of column decoders, and every two adjacent of said column-selecting lines are controlled by one column decoder.

Claim 18

The semiconductor memory according to claim 11, characterized in that each of said row decoders selects one of the two sub-blocks and then one of the word lines extending over the sub-block selected.

Claim 19

The semiconductor memory according to claim 11, characterized in that said data input/output region is rectangular, provided on a center part of said memory chip and extending parallel to the rows of memory cells.

Claim 20

The semiconductor memory according to claim 19, characterized in that said data buses extend parallel to the columns of memory cells, on both sides of said data input/output region.

Claim 21

The semiconductor memory according to claim 20, characterized in that said sub-banks are located on both sides of said data buses.

Claim 22

The semiconductor memory according to claim 21, characterized in that said sub-banks are eight banks which are arranged in four rows and two columns.

Claim 23

The semiconductor memory according to claim 11, characterized in that said data input/output region is located at the first end of every column of memory cells.

Claim 24

The semiconductor memory according to claim 23, characterized in that said data buses are provided on a first side of said data input/output region and extend parallel to the columns of memory cells and at right angles to said data input/output region.

Claim 25

The semiconductor memory according to claim 24, characterized in that said sub-banks are provided on both sides of said data buses which are spaced apart along the rows of memory cells.

Claim 26

The semiconductor memory according to claim 25, characterized in that said sub-banks are eight banks which are arranged in four rows and two columns.

Claim 27

A semiconductor memory according comprising: A. a memory chip (10); B. a plurality of banks (11-0 to 11-3) arranged on said memory chip, for storing and outputting multi-bit data, independently of one another, each comprising: a. a plurality of memory-cell blocks (BLa, BLb, BLc, BLd), each comprising two sub-blocks (CAL, CAR), sense amplifiers (SA), word lines (17), data lines (14) and column-selecting lines (15), each of said sub-blocks composed of one memory cell array, said sense amplifiers located between said two sub-blocks, said word lines, data lines and column-selecting lines arranged on the memory cell arrays constituting said two sub-blocks, said memory-cell blocks spaced apart along columns of memory cells and the column-selecting lines and data lines, and said sub-blocks spaced apart also along the columns of memory cells; b. at least one column decoder (CD0, CD1) located at a first end of every column of memory cells and connected to said column-selecting lines; c. a plurality of row decoders (RD) located at a first end of every row of memory cells along which said word line extend, and connected to said word lines, each of said row decoders provided for one memory-cell block; d. a plurality of DQ buffers (DQ) located at a second end of every row of memory cells; e. a cell-array controller (CAC) located at the first end of very row of memory cells, for controlling the reading and writing of the multi-bit data; C. a data input/output region (12) provided on said memory chip, for receiving multi-bit data from an external device and outputting multi-bit data to an external device; and D. a data bus (13) provided for said plurality of banks, extending parallel to the columns of memory cells, for transferring multi-bit data between said plurality of banks, one the one hand, and said data input/output region, on the other.

Claim 28

The semiconductor memory according to claim 27, characterized in that each of said banks has local DQ-line pairs (18a) located among said sub-blocks, extending parallel to the rows of memory cells and connected to said sense amplifiers, and global DQ-line pairs (18b) provided on said memory-cell blocks, extending parallel to the columns of memory cells and connecting said local DQ-line pairs to said DQ buffers.

Claim 29

The semiconductor memory according to claim 28, characterized by further comprising switches (21) arranged among said local DQ-line pairs, on the one hand, and said global DQ-line pairs, on the other.

Claim 30

The semiconductor memory according to claim 29, characterized in that each of said switches is composed of an N-channel MOS transistor.

Claim 31

The semiconductor memory according to claim 27, characterized in that each of said banks has a bank-selecting circuit at the second end of every row of memory cells, and said bank-selecting circuit connects one of said banks to said data bus and disconnects the remaining banks from said data bus, in order to output and receive the multi-bit data.

Claim 32

The semiconductor memory according to claim 27, characterized in that said plurality of banks are four banks which are arranged in two rows and two columns.

Claim 33

The semiconductor memory according to claim 27, characterized by further comprising column-selecting switches located among said sub-blocks and connected to said column-selecting lines.

Claim 34

The semiconductor memory according to claim 27, characterized in that said data input/output region is located at the first end of every row of memory cells.

Claim 35

The semiconductor memory according to claim 27, characterized in that said data input/output region is rectangular, provided on a center part of said memory chip and extending parallel to the columns of memory cells.

Claim 36

The semiconductor memory according to claim 27, characterized in that said data input/output region has a plurality of data input/output circuits for receiving and outputting bits of the multi-bit data at the same time.

Claim 37

The semiconductor memory according to claim 27, characterized in that said data bus is provided on a center part of said memory chip and extending parallel to the columns of memory cells, and some of said banks are located on a first side of said data bus and the remaining banks are located on a second side of said data bus.

Claim 38

The semiconductor memory according to claim 27, characterized in that said column-selecting lines are divided into groups which are completely separated from one another, and each of said banks has a plurality of column decoders for controlling the groups of column-selecting lines, respectively.

Claim 39

The semiconductor memory according to claim 27, characterized in that each of said row decoders selects one of the two sub-blocks and then one of the word lines extending over the sub-block selected.

Claim 40

The semiconductor memory according to claim 27, characterized in that at least one of said column decoders has a first function of selecting one of said column-selecting lines and a second function of selecting at least two of said column-selecting lines, and said first and second functions are switched from one to the other in accordance with a control signal.

Claim 41

A semiconductor memory according comprising: A. a memory chip (10); B. a plurality of main banks (11-0 to 11-3) arranged on said memory chip, for storing and outputting multi-bit data, independently of one another, each composed of a plurality of sub-banks (11-0-#0, 11-0-#1, to 11-3-#0, 11-3-#1), each of which comprises: a. a plurality of memory-cell blocks (BLa, BLb, BLc, BLd), each comprising two sub-blocks (CAL, CAR), sense amplifiers (SA), word lines (17), data lines (14) and column-selecting lines (15), each of said sub-blocks composed of one memory cell array, said sense amplifiers located between said two sub-blocks, said word lines, data lines and column-selecting lines arranged on the memory cell arrays constituting said two sub-blocks, said memory-cell blocks spaced apart along columns of memory cells and the column-selecting lines and data lines, and said sub-blocks spaced apart also along the columns of memory cells; b. at least one column decoder (CD0 to CD1) located at a first end of every column of memory cells and connected to said column-selecting lines; c. a plurality of row decoders (RD) located at a first end of every row of memory cells along which said word line extend, and connected to said word lines, each of said row decoders provided for one memory-cell block; d. a plurality of DQ buffers (DQ) located at a second end of every column of memory cells; e. a cell-array controller (CAC) located at the first end of very row of memory cells, for controlling the reading and writing of the multi-bit data; C. a data input/output region (12) provided on said memory chip, for receiving multi-bit data from an external device and outputting multi-bit data to an external device; and D. a plurality of data buses (13a, 13b) provided for at least two of said sub-banks, extending parallel to the rows of memory cells, for transferring multi-bit data between said sub-banks, one the one hand, and said data input/output region, on the other.

Claim 42

The semiconductor memory according to claim 41, characterized in that each of said sub-banks has local DQ-line pairs (18a) located among said sub-blocks, extending parallel to the rows of memory cells and connected to said sense amplifiers, and global DQ-line pairs (18b) provided on said memory-cell blocks, extending parallel to the columns of memory cells and connecting said local DQ-line pairs to said DC buffers.

Claim 43

The semiconductor memory according to claim 42, characterized by further comprising switches (21) arranged among said local DQ-line pairs, on the one hand, and said global DQ-line pairs, on the other.

Claim 44

The semiconductor memory according to claim 43, characterized in that each of said switches is composed of an N-channel MOS transistor.

Claim 45

The semiconductor memory according to claim 42, characterized in that each of said sub-banks has a bank-selecting circuit at the second end of every row of memory cells, and said bank-selecting circuit connects at least two of said banks constituting all main banks to said data buses and disconnects the remaining sub-banks from said data buses, in order to output and receive the multi-bit data.

Claim 46

The semiconductor memory according to claim 45, characterized in that data items are transferred through difference data buses, between the sub-banks selected, one the one hand, and said data input/output region, on the other.

Claim 47

The semiconductor memory according to claim 41, characterized by further comprising column-selecting switches located among said sub-blocks and connected to said column-selecting lines.

Claim 48

The semiconductor memory according to claim 41, characterized in that each of said main banks is composed of an n number of sub-banks, and said data input/output region has a plurality of data input/output circuits for receiving and outputting n times the bits of said multi-bit data, at the same time.

Claim 49

The semiconductor memory according to claim 41, characterized in that said column-selecting lines are divided into groups which are completely separated from one another, and each of said banks has a plurality of column decoders for controlling the groups of column-selecting lines, respectively.

Claim 50

The semiconductor memory according to claim 41, characterized in that each of said row decoders selects one of the two sub-blocks and then one of the word lines extending over the sub-block selected.

Claim 51

The semiconductor memory according to claim 41, characterized in that said data input/output region is rectangular, provided on a center part of said memory chip and extending parallel to the columns of memory cells.

Claim 52

The semiconductor memory according to claim 51, characterized in that said data buses are provided on both sides of said data input/output region and extend parallel to the rows of memory cells and at right angles to said data input/output region.

Claim 53

The semiconductor memory according to claim 52, said data buses extend parallel to the columns of memory cells and said sub-banks are located on both sides of said data buses.

Claim 54

The semiconductor memory according to claim 53, characterized in that said sub-banks are eight banks which are arranged in four rows and two columns.

Claim 55

The semiconductor memory according to claim 41, characterized in that said data input/output region is located at the first end of every row of memory cells.

Claim 56

The semiconductor memory according to claim 55, characterized in that said data input/output region extends parallel to the columns of memory cells and said data buses extend parallel to the rows of memory cells, on the first side of said data input/output region.

Claim 57

The semiconductor memory according to claim 56, said data buses extend parallel to the rows of memory cells and said sub-banks are located on both sides of said data buses.

Claim 58

The semiconductor memory according to claim 57, characterized in that said sub-banks are eight banks which are arranged in four rows and two columns.

Claim 59

A semiconductor memory according comprising: A. a memory chip (10); B. a plurality of main banks (11-0 to 11-3) arranged on said memory chip, for storing and outputting multi-bit data, independently of one another, each composed of a plurality of sub-banks (11-0-#0, 11-0-#1, to 11-3-#0, 11-3-#1), each of which comprises: a. a plurality of memory-cell blocks (BLa, BLb, BLc, BLd), each comprising two sub-blocks (CAL, CAR), sense amplifiers (SA), word lines (17), data lines (14) and column-selecting lines (15), each of said sub-blocks composed of one memory cell array, said sense amplifiers located between said two sub-blocks, said word lines, data lines and column-selecting lines arranged on the memory cell arrays constituting said two sub-blocks, said memory-cell blocks spaced apart along columns of memory cells and the column-selecting lines and data lines, and said sub-blocks spaced apart also along the columns of memory cells; b. at least one column decoder (CD0, CD1) located at a first end of every column of memory cells and connected to said column-selecting lines; c. a plurality of row decoders (RD) located at a first end of every row of memory cells along which said word line extend, and connected to said word lines, each of said row decoders provided for one memory-cell block; d. a plurality of DQ buffers (DQ) located at a second end of every row of memory cells, each of said DQ buffers provided for one memory-cell block; e. a cell-array controller (CAC) located at the first end of very row of memory cells, for controlling the reading and writing of the multi-bit data; C. a plurality of data input/output regions (12a, 12b) provided on said memory chip, for receiving multi-bit data from an external device and outputting multi-bit data to an external device; and D. a plurality of data buses (13a, 13b, 13c, 13d) provided for at least two of said sub-banks, extending parallel to the rows of memory cells, for transferring multi-bit data between said sub-banks, one the one hand, and said data input/output regions, on the other, wherein said input/output regions are spaced apart along the rows of memory cells, said data buses are arranged on both sides of each of said data input/output regions and spaced apart along the columns of memory cells, and said sub-banks are arranged on both sides of each of said data buses.

Claim 60

The semiconductor memory according to claim 59, characterized in that each of said sub-banks has local DQ-line pairs (18a) located among said sub-blocks, extending parallel to the rows of memory cells and connected to said sense amplifiers, and global DQ-line pairs (18b) provided on said memory-cell blocks, extending parallel to the columns of memory cells and connecting said local DQ-line pairs to said DC buffers.

Claim 61

The semiconductor memory according to claim 60, characterized by further comprising switches (21) arranged among said local DQ-line pairs, on the one hand, and said global DQ-line pairs, on the other.

Claim 62

The semiconductor memory according to claim 61, characterized in that each of said switches is composed of an N-channel MOS transistor.

Claim 63

The semiconductor memory according to claim 59, characterized in that each of said sub-banks has a bank-selecting circuit at the second end of every column of memory cells, and said bank-selecting circuit connects at least two of said banks constituting all main banks to said data buses and disconnects the remaining sub-banks from said data buses, in order to output and receive the multi-bit data.

Claim 64

The semiconductor memory according to claim 63, characterized in that data items are transferred through difference data buses, between the sub-banks selected, one the one hand, and said data input/output regions, on the other.

Claim 65

The semiconductor memory according to claim 59, characterized by further comprising column-selecting switches located among said sub-blocks and connected to said column-selecting lines.

Claim 66

The semiconductor memory according to claim 59, characterized in that each of said main banks is composed of an n number of sub-banks, and each of said data input/output regions has a plurality of data input/output circuits for receiving and outputting the bits of said multi-bit data, at the same time.

Claim 67

The semiconductor memory according to claim 59, characterized in that said column-selecting lines are divided into groups which are completely separated from one another, and each of said sub-banks has a plurality of column decoders for controlling the groups of column-selecting lines, respectively.

Claim 68

The semiconductor memory according to claim 59, characterized in that each of said row decoders selects one of the two sub-blocks and then one of the word lines extending over the sub-block selected.

Claim 69

The semiconductor memory according to claim 59, characterized in that said sub-banks are eight banks which are arranged in four rows and two columns.

Claim 70

The semiconductor memory according to claim 59, characterized in that each of said main banks operate in synchronism with a clock signal to store and output the multi-bit data.

Claim 71

A test circuit for testing a semiconductor memory comprising a memory cell array (CAL, CAR) composed of a plurality of memory-cell blocks, data-writing means (BW) for writing bits of data simultaneously into memory cells of at least one of the memory-cell blocks, and a register (35) for holding the data to be written into said at least one of the memory-cell blocks, said test circuit comprising: write/read means (DBWBF, DBSAMP, 30) for writing the data held in said register into the memory cells of said at least one of the memory-cell blocks and for reading data from said memory cells; comparing means (34, 100) for comparing the data held in said register with the data read from said memory cells to determine whether the semiconductor memory is flawless and for generating data representing whether the semiconductor memory is flawless; and an output circuit (200) for outputting the data generated by said comparing means, from the semiconductor memory.

Claim 72

A test circuit for testing a semiconductor memory comprising a memory cell array composed of a plurality of memory-cell blocks (CAL, CAR), data-writing means (BW) for writing n-bit data simultaneously into memory cells of n memory cell-blocks among said memory-cell blocks, and a register (35) for holding the n-bit data to be written into the n memory cell blocks, said semiconductor memory comprising: write/read means (DBWBF, DBSAMP, 30) for writing the data held in said register into the memory cells of said n memory-cell blocks and for reading data from said memory cells; comparing means (34) for comparing the n-bit data held in said register with the n-bit data read from said memory cells to determine whether the semiconductor memory is flawless and for generating n-bit data representing whether the semiconductor memory is flawless; and an output circuit (200) for outputting the n-bit data generated by said comparing means, from the semiconductor memory.

Claim 73

The test circuit according to claim 72, characterized by further comprising latch means (LATCH) for holding the n-bit data generated by said comparing means, and switching means (37, 38) for supplying n bits of the data generated by said comparing means, sequentially to said output circuit when said comparing means determines that the semiconductor memory is defective.

Claim 74

The test circuit occurring to claim 72, characterized in that said semiconductor memory is an n-bit type one designed to store and output n bits at the same time and has n output pads for use in ordinary operating mode, and said output circuit is connected to one of the n output pads.

Claim 75

A data transfer system comprising: a plurality of memory-cell blocks (BL0 to BLn) arranged in a line parallel to columns of memory cells, each comprising: first and second switch arrays (41a, 41b) each having a plurality of switches arranged in the form of a matrix; first row decoders (42a) provided at one of sides of said switch array (41a) which extend at right angles to row of switches; a local DQ line (50-1) provided to one side of switch array (41a, 41b) and extending parallel to the rows of switches; and a data line (45a) connected to switches of said switch array (41a), for supplying data to said local DQ line (50-1); a global DQ line (51-0) extending over said switch blocks (BL0 to BLn), in parallel to the column of switches, and connected at one end to said local DQ line (50-0); a column decoder (43) provided at one side of said switch blocks (BL0 to BLn), for selecting column of switches provided in said switch blocks (BL0 to BLn); and a data input/output circuit (52) provided at one side of said switch blocks (BL0 to BLn) and connected to the other end of said global DQ line (51-0), for receiving and outputting data.

Claim 76

The data transfer system according to claim 75, characterized by further comprising column-selecting lines (49) located on said switch array.

Claim 77

The data transfer system according to claim 76, characterized by further comprising column-selecting switches (48a, 48b) located one side of said switch array, and connected to said column-selecting lines.

Claim 78

The data transfer system according to claim 75, characterized by further comprising registers (47a, 47b) located one side of said switch arrays, and connected between said data line and said local DQ line.

Claim 79

The data transfer system according to claim 75, characterized in that said data input/output circuits receiving and outputting bits of multi-bit data at the same time.

Claim 80

A memory system according comprising: A. a memory chip (10); B. a plurality of banks (11-0 to 11-3) arranged on said memory chip, for storing and outputting multi-bit data in synchronism with a clock signal, independently of one another, each comprising: a. a plurality of memory-cell blocks (BLa, BLb, BLc, BLd), each comprising two sub-blocks (CAL, CAR), sense amplifiers (SA), word lines (17), data lines (14) and column-selecting lines (15-0, 15-1), each of said sub-blocks composed of one memory cell array, said sense amplifiers located between said two sub-blocks, said word lines, data lines and column-selecting lines arranged on the memory cell arrays constituting said two sub-blocks, said memory-cell blocks spaced apart along columns of memory cells and the column-selecting lines and data lines, and said sub-blocks spaced apart also along the columns of memory cells; b. at least one column decoder (CD0, CD1) located at at least a first end of every column of memory cells and connected to said column-selecting lines; c. a plurality of row decoders (RD) located at a first end of every row of memory cells along which said word line extend, and connected to said word lines, each of said row decoders provided for one memory-cell block; d. a plurality of DQ buffers (DQ) located at a second end of every row of memory cells, each of said DQ buffers provided for one memory-cell block; e. a cell-array controller (CAC) located at a second end of very row of memory cells, for controlling the reading and writing of the multi-bit data; C. a data input/output region (12) provided on said memory chip, for receiving multi-bit data from an external device and outputting multi-bit data to an external device; D. a data bus (13) provided for said plurality of banks, extending parallel to the columns of memory cells, for transferring multi-bit data between said plurality of banks, one the one hand, and said data input/output region, on the other; E. a CPU chip generating said clock signal; and F. an I/O bus connecting between said memory chip and said CPU chip.

Claim 81

A memory system according comprising: A. a memory chip (10); B. a plurality of main banks (11-0 to 11-3) arranged on said memory chip, for storing and outputting multi-bit data in synchronism with a clock signal, independently of one another, each composed of a plurality of sub-banks (11-0-#0, 11-0-#1, to 11-3-#0, 11-3-#1), each of which comprises: a. a plurality of memory-cell blocks (BLa, BLb, BLc, BLd), each comprising two sub-blocks (CAL, CAR), sense amplifiers (SA), word lines (17), data lines (14) and column-selecting lines (15-0 to 15-3), each of said sub-blocks composed of one memory cell array, said sense amplifiers located between said two sub-blocks, said word lines, data lines and column-selecting lines arranged on the memory cell arrays constituting said two sub-blocks, said memory-cell blocks spaced apart along columns of memory cells and the column-selecting lines and data lines, and said sub-blocks spaced apart also along the columns of memory cells; b. at least one column decoder (CD0 to CD3) located at at least a first end of every column of memory cells and connected to said column-selecting lines; c. a plurality of row decoders (RD) located at a first end of every row of memory cells along which said word line extend, and connected to said word lines, each of said row decoders provided for one memory-cell block; d. a plurality of DQ buffers (DQ) located at a second end of every row of memory cells, each of said DQ buffers provided for one memory-cell block; e. a cell-array controller (CAC) located at a second end of very row of memory cells, for controlling the reading and writing of the multi-bit data; C. a data input/output region (12) provided on said memory chip, for receiving multi-bit data from an external device and outputting multi-bit data to an external device; D. a plurality of data buses (B) provided for at least two of said sub-banks, extending parallel to the columns of memory cells, for transferring multi-bit data between said sub-banks, one the one hand, and said data input/output region, on the other; E. a CPU chip generating said clock signal; and F. an I/O bus connecting between said memory chip and said CPU chip.

Claim 82

A memory system according comprising: A. a memory chip (10); B. a plurality of banks (11-0 to 11-3) arranged on said memory chip, for storing and outputting multi-bit data in synchronism with a clock signal, independently of one another, each comprising: a. a plurality of memory-cell blocks (BLa, BLb, BLc, BLd), each comprising two sub-blocks (CAL, CAR), sense amplifiers (SA), word lines (17), data lines (14) and column-selecting lines (15), each of said sub-blocks composed of one memory cell array, said sense amplifiers located between said two sub-blocks, said word lines, data lines and column-selecting lines arranged on the memory cell arrays constituting said two sub-blocks, said memory-cell blocks spaced apart along columns of memory cells and the column-selecting lines and data lines, and said sub-blocks spaced apart also along the columns of memory cells; b. at least one column decoder (CD0, CD1) located at a first end of every column of memory cells and connected to said column-selecting lines; c. a plurality of row decoders (RD) located at a first end of every row of memory cells along which said word line extend, and connected to said word lines, each of said row decoders provided for one memory-cell block; d. a plurality of DQ buffers (DQ) located at a second end of every row of memory cells; e. a cell-array controller (CAC) located at the first end of very row of memory cells, for controlling the reading and writing of the multi-bit data; C. a data input/output region (12) provided on said memory chip, for receiving multi-bit data from an external device and outputting multi-bit data to an external device; D. a data bus (13) provided for said plurality of banks, extending parallel to the columns of memory cells, for transferring multi-bit data between said plurality of banks, one the one hand, and said data input/output region, on the other; E. a CPU chip generating said clock signal; and F. an I/O bus connecting between said memory chip and said CPU chip.

Claim 83

A memory system according comprising: A. a memory chip (10); B. a plurality of main banks (11-0 to 11-3) arranged on said memory chip, for storing and outputting multi-bit data in synchronism with a clock signal, independently of one another, each composed of a plurality of sub-banks (11-0-#0, 11-0-#1, to 11-3-#0, 11-3-#1), each of which comprises: a. a plurality of memory-cell blocks (BLa, BLb, BLc, BLd), each comprising two sub-blocks (CAL, CAR), sense amplifiers (SA), word lines (17), data lines (14) and column-selecting lines (15), each of said sub-blocks composed of one memory cell array, said sense amplifiers located between said two sub-blocks, said word lines, data lines and column-selecting lines arranged on the memory cell arrays constituting said two sub-blocks, said memory-cell blocks spaced apart along columns of memory cells and the column-selecting lines and data lines, and said sub-blocks spaced apart also along the columns of memory cells; b. at least one column decoder (CD0 to CD1) located at a first end of every column of memory cells and connected to said column-selecting lines; c. a plurality of row decoders (RD) located at a first end of every row of memory cells along which said word line extend, and connected to said word lines, each of said row decoders provided for one memory-cell block; d. a plurality of DQ buffers (DQ) located at a second end of every column of memory cells; e. a cell-array controller (CAC) located at the first end of very row of memory cells, for controlling the reading and writing of the multi-bit data; C. a data input/output region (12) provided on said memory chip, for receiving multi-bit data from an external device and outputting multi-bit data to an external device; D. a plurality of data buses (13a, 13b) provided for at least two of said sub-banks, extending parallel to the rows of memory cells, for transferring multi-bit data between said sub-banks, one the one hand, and said data input/output region, on the other; E. a CPU chip generating said clock signal; and F. an I/O bus connecting between said memory chip and said CPU chip.

Claim 84

A memory system according comprising: A. a memory chip (10); B. a plurality of main banks (11-0 to 11-3) arranged on said memory chip, for storing and outputting multi-bit data in synchronism with a clock signal, independently of one another, each composed of a plurality of sub-banks (11-0-#0, 11-0-#1, to 11-3-#0, 11-3-#1), each of which comprises: a. a plurality of memory-cell blocks (BLa, BLb, BLc, BLd), each comprising two sub-blocks (CAL, CAR), sense amplifiers (SA), word lines (17), data lines (14) and column-selecting lines (15), each of said sub-blocks composed of one memory cell array, said sense amplifiers located between said two sub-blocks, said word lines, data lines and column-selecting lines arranged on the memory cell arrays constituting said two sub-blocks, said memory-cell blocks spaced apart along columns of memory cells and the column-selecting lines and data lines, and said sub-blocks spaced apart also along the columns of memory cells; b. at least one column decoder (CD0, CD1) located at a first end of every column of memory cells and connected to said column-selecting lines; c. a plurality of row decoders (RD) located at a first end of every row of memory cells along which said word line extend, and connected to said word lines, each of said row decoders provided for one memory-cell block; d. a plurality of DQ buffers (DQ) located at a second end of every row of memory cells, each of said DQ buffers provided for one memory-cell block; e. a cell-array controller (CAC) located at the first end of very row of memory cells, for controlling the reading and writing of the multi-bit data; C. a plurality of data input/output regions (12a, 12b) provided on said memory chip, for receiving multi-bit data from an external device and outputting multi-bit data to an external device; D. a plurality of data buses (13a, 13b, 13c, 13d) provided for at least two of said sub-banks, extending parallel to the rows of memory cells, for transferring multi-bit data between said sub-banks, one the one hand, and said data input/output regions, on the other, wherein said input/output regions are spaced apart along the rows of memory cells, said data buses are arranged on both sides of each of said data input/output regions and spaced apart along the columns of memory cells, and said sub-banks are arranged on both sides of each of said data buses; and E. a CPU chip generating said clock signal; and F. an I/O bus connecting between said memory chip and said CPU chip.