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JPH03212955A Expired / Lapsed JP ⏱️ 0.0 years remaining

Semiconductor device

Assignee: JFE Steel Corp
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Filing: 1990-01-18
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Granted: —
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Expires: 2010-01-18
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Abstract

Abstract PURPOSE:To prevent malfunctions by a method wherein the wiring of a logic circuit group is separated from the wiring of an output buffer transistor group. CONSTITUTION:Pads P14a, P16a of power-supply lines 14a, 16a are independent of each other and are connected to independent power-supply pins Vdd1, Vdd2 by using wires W10, W12. Consequently, the lines 14a, 16a are separated and are independent of each other on a semiconductor integrated circuit 8. Since pads P14b, P16b of connecting lines 14b, 16b are connected to independent ground pins VSS1, VSS2 by using wires W14, W16, the lines 14b, 16b are separated and are independent of each other on the circuit 8. The pins VSS1, VSS2 are connected to a ground line GND which has been fixed to a stable ground potential; a stable positive power supply is fed to the pins Vdd1, Vdd2. Thereby, a ground noise by a switching operation of output buffer transistor groups 12a, 12b is absorbed by the line GND via the wire W14 and the pin VSS1 from the pad P14b, and is not propagated to an internal circuit 10. Thereby, the malfunction of a logic circuit is prevented surely and a stable circuit operation can be secured.

Inventors

  • 👤 Kikuo Kimura
  • 👤 木村 貴久男

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-11-01 17:57
CPC Classifications
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