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Patent JPS57756A successfully refreshed from Google Patents.
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JPS57756A Expired / Lapsed JP ⏱️ 0.0 years remaining

Data processor

Assignee: Hitachi Ltd
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Filing: 1980-06-04
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Granted: —
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Expires: 2000-06-04
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Abstract

Abstract PURPOSE: To reduce the memory capacity of a data processor which performs pipeline processing, by executing an operand by the same microinstruction in both register direct mode and memory reference mode. CONSTITUTION: Between an instruction setup unit 100 and an instruction execution unit 101, a register 300 for communication is provided and when an operand is supplied in register direct mode, the instruction setup unit 100 accesses a general register 114 to transfer and fetch selectively the contents of the register as the operand into the register 300 for communication in advance. When an addressing mode is a memory reference mode, the operand of this register 300 is read into the instruction execution unit 101. Therefore, a microprogram executing instructions is made common. COPYRIGHT: (C)1982,JPO&Japio

Inventors

  • 👤 Hidekazu Matsumoto
  • 👤 Tadaaki Bando

Bibliographic Details

Application Number —
Jurisdiction JP
Data Source google_patents
Last Synchronized 2026-10-31 05:58
CPC Classifications
—

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