Mos transistor output circuit

Abstract

Abstract PURPOSE:To generate an output high level to driven directly a CMOS load and to obtain an output circuit which is not much affected by the fluctuation of a manufacturing process attaining a reduction of access time by installing a pull-up transistor and a pull-up driving circuit. CONSTITUTION:When I/O is the high level and I/O is the low level, a nodal point N1 becomes the high level and a nodal point N2 becomes the low level, and therefore, an output terminal OUT will not change while a Vcc level is kept. Reversely, when an input I/O is the low and I/O is the high level, the nodal point N1 preserves the low level and N2 is changed to the high level. The high level of an output terminal OUT is reset by a transistor Q2 and simultaneously, the gate electric potential of a pull-up transistor Q30 is reset to the low level by conducting a transistor Q34 with the high of the nodal point N2. Consequently, the time until the output terminal OUT becomes the low level is an access time, and the maximum value of the low level of a normal input for a CMOS load is 1.35 V (electric power source voltage 4.5VX0.3), and therefore, a quick access time can be obtained.

Inventors

• 👤 Shoji Ishimoto
• 👤 石本　章二

Bibliographic Details