Precision controlled arithmetic processing system

Claim 2

Apparatus for performing arithmetic operations on multidigit numbers of a predetermined precision comprising: means for detecting the predetermined precision of each multidigit number; means for performing the arithmetic operations; means coupled to both said detecting means and said performing means for determining the number of digits within the degree of precision of the output of said performing means based on the predetermined precision of each of the input numbers to said detecting means and the kind of arithmetic operation being performed by said performing means; and means responsive to said determining means for eliminating the digits not within said degree of precision of the resultant output.

Claim 3

In a variable field length arithmetic processing system, including a processor, to which two multidigit operands are supplied for arithmetic processing, each operand being associated with a precision defining flag which is of a first value when the operand is of finite precision or a second value when the operand is of infinite precision, the improvement comprising control means, coupled to said processor and responsive to the operands and the precision defining flags associated therewith, for controlling said processor when performing addition or subtraction to process said operands until the rightmost digit of the shorter of the two operands is processed when the precision defining flags, associated with both operands, are of said first value, or until the rightmost digit of the operand of finite precision is processed if the other operand is of infinite precIsion, or until the rightmost digit of the longer of the two operands is processed if the two operands are both of infinite precision.

Claim 4

In a variable field length arithmetic processing system, including a processor, to which two multidigit operands are supplied for arithmetic processing, each operand being associated with a precision defining flag which is of a first value when the operand is of finite precision or a second value when the operand is of infinite precision, the improvement comprising control means, coupled to said processor and responsive to the operands and the precision defining flags associated therewith, for controlling said processor when performing addition or subtraction to process said operands until the rightmost digit of the shorter of the two operands is processed when the precision defining flags, associated with both operands, are of said first value, or until the rightmost digit of the operand of finite precision is processed if the other operand is of infinite precIsion, or until the rightmost digit of the longer of the two operands is processed if the two operands are both of infinite precision.

Claim 5

The arithmetic processing system as recited in claim 2 further including means responsive to the precision defining flags of said two operands for associating with the output of said processor, a precision defining flag which is of said first value when at least one of said operands is of finite precision or of said second value when both operands are of infinite precision.

Claim 6

The arithmetic processing system as recited in claim 2 further including logic means coupled to respond to at least said operands and a signal representing multiplication and division operations for providing a count which represents the number of digits of the shorter of the two operands when both operands are of finite precision, the count representing the number of digits of the operand which is of finite precision when the other operand is of infinite precision, or the count equaling a preselected value when both operands are of infinite precision.

Claim 7

The arithmetic processing system as recited in claim 4 further including means responsive to the precision defining flags of said two operands for associating, with the output of said processor, a precision defining flag which is of said first value when at least one of said operands is of finite precision or of said second value when both operands are of infinite precision.

Claim 8

The arithmetic processing system as recited in claim 5 further including means for providing an end of cycle signal as a function of the sensing of either end-of-operand flags associated with said operands, or said precision defining flags associated with said operands.

Claim 9

In an arithmetic processing system of the type having first and second input means for receiving first and second multidigit numbers respectively, and a processing unit supplied with said first and second numbers for performing a selected arithmetic operation thereon to provide a resultant output number in accordance therewith, the improvement comprising: first means coupled to said first and second input means for sensing the degree of precision of each of said first and second numbers; and control means coupled to said first means and to said processing unit for controlling the operation of said processing unit as a function of the degree of precision of said first and second numbers.

Claim 10

In an arithmetic processing system of the type having first and second input means for receiving first and second multidigit numbers respectively, and a processing unit supplied with said first and second numbers for performing a selected arithmetic operation thereon to provide a resultant output number in accordance therewith, the improvement comprising: first means coupled to said first and second input means for sensing the degree of precision of each of said first and second numbers; and control means coupled to said first means and to said processing unit for controlling the operation of said processing unit as a function of the degree of precision of said first and second numbers.

Claim 11

The system as recited in claim 7 wherein the digits of each of said first and second numbers are supplied in series high-to-low order whereby during each processing cycle the highest order digit of each number is first to be supplied and wherein the rightmost digit of each number is followed by a precision defining flag which is of a first value when the number is of finite precision and of a second value when said number is of infinite precision, and said first means include gating means for providing an end of processing cycle signal upon sensing a precision defining flag of said first value associated with either of said numbers or upon sensing a precision defining flag of said second value associated with one of said numbers after having previously sensed a similar flag associated with the other number, said control means including means for supplying said end of processing cycle signal to said processing unit to terminate the operation thereof, said control unit further including gating means for inserting a precision defining flag after the resultant output number from said processing unit, the value of the inserted precision defining flag being a function of the value of the precision defining flags of said first and second numbers.

Claim 12

The system as recited in claim 8 further including means for providing a count to said control unit representing the number of digits of the shortest of said numbers which is of finite precision and for providing a preselected maximum count when both of said numbers are of infinite precision.

Claim 13

The system as recited in claim 7 wherein each of said first and second numbers includes an end-of-number flag preceding the leftmost digit thereof and further including means providing either a finite precision defining signal or an infinite precision defining signal when the precision of said number is finite or infinite respectively, said system including means for providing a count indicative of the number of digits of the shorter of the two numbers which is of finite precision, or a preselected maximum count when both said first and second numbers are of infinite precision.

Claim 14

The system as recited in claim 10 further including first logic means within said first sensing means for sensing the end-of-number flag associated with each of said numbers to provide an end-of-cycle signal to said processing unit, upon sensing the end-of-number flags of both of said numbers, and second logic means within said control means for controlling the number of digits of the resultant output number as a function of the precisions of said numbers.

Claim 15

The system as recited in claim 11 wherein said second logic means include means which control said resultant output number so that the rightmost digit thereof corresponds to the rightmost digit of the shortest number when both said numbers are of finite precision, or to the rightmost digit of one of said numbers which is of finite precision if the other number is of infinite precision, or to the rightmost digit of the longer of the two numbers when both are of infinite precision, when said processing unit is operated in addition or subtraction, said second logic means further including means utilizing the count in said counting means for limiting the number of digits of the resultant output number to equal said count, when said processing unit is operable in multiplication and division.

Claim 16

In an arithmetic processing system of the type having first and second input means for receiving first and second multidigit numbers respectively, and a processing unit supplied with said first and second numbers for performing a selected arithmetic operation thereon and for providing a resultant output number in accordance therewith, the improvement comprising: first means for sensing the degree of precision of each of said first and second numbers; and control means coupled to said first means and to said processing unit and responsive to a signal indicating addition or subtraction operation for limiting the processing until the rightmost digit is processed of the shorter of the two numbers when both numbers are of finite precision or until the rightmost digit of the least precise number is processed, when one number is of finite precision and the other number is of infinite precision, or until the rightmost digit is processed of the longer of the two numbers, when both numbers are of infinite precision.

Claim 17

In an arithmetic processing system of the type having first and second input means for receiving first and second multidigit numbers respectively, and a processing unit supplied with said first and second numbers for performing a selected arithmetic operation thereon and for providing a resultant output number in accordance therewith, the improvement comprising: first means for sensing the degree of precision of each of said first and second numbers; and control means coupled to said first means and to said processing unit and responsive to a signal indicating addition or subtraction operation for limiting the processing until the rightmost digit is processed of the shorter of the two numbers when both numbers are of finite precision or until the rightmost digit of the least precise number is processed, when one number is of finite precision and the other number is of infinite precision, or until the rightmost digit is processed of the longer of the two numbers, when both numbers are of infinite precision.

Claim 18

The system as recited in claim 13 further including logic means for associating with said resultant output number a precision defining flag, said flag representing finite precision when at least one of said numbers is of finite precision, or said flag representing infinite precision when both of said numbers are of infinite precision.

Claim 19

The system as recited in claim 13 wherein said system further includes means responsive to a signal indicating multiplication or division operation and counting means for providing a count representing the number of digits of the shorter of the two numbers when both numbers are of finite precision, the count representing the number of digits of the least precise number if the numbers are of different degrees of precision, or the number equaling a preselected maximum value when both numbers are of infinite precision.

Claim 20

The system as recited in claim 15 further including logic means for associating with said resultant output number a precision defining flag, said flag being of a first value representing finite precision when at least one of said numbers is of finite precision, and said Flag being of a second value representing infinite precision when both of said numbers are of infinite precision.