Patent US3569744A successfully refreshed from Google Patents.
US3569744A
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Resettable monostable pulse generator
Assignee: National Aeronautics and Space Administration
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Filing: 1968-08-30
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Granted: 1971-03-09
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Expires: 1988-08-30
Abstract
Abstract This disclosure describes a resettable monostable pulse generator including a charge rundown-timing circuit. The charge rundown-timing circuit includes a capacitor that is charged to a peak value by a random pulse from a constant amplitude pulse source. After being charged, the capacitor immediately starts to discharge toward zero. In addition, an output pulse generator starts to generate an output pulse as soon as the capacitor is charged to its peak value and continues to generate the output pulse until the charge drops to a predetermined level. If a second pulse from the constant amplitude pulse source occurs during this rundown period, the capacitor is again charged to its peak value. This ''''reset'''' pulse prevents termination of the output pulse and recycles the termination time of the output pulse (pulse width) to be measured from the inception of the last reset pulse. Each time a ''''reset'''' pulse occurs during a rundown period, the capacitor is recharged to its peak value; hence, the output pulse can exist for a short or long period of time depending on the occurrence of random reset pulses. The invention described herein was made by an employee of the United States Government and may be manufactured and used by or for the Government for governmental purposes without the payment of any royalties thereon or therefor.
Inventors
- 👤 Norman M Garrahan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 20:17
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/26; H03K3/28; H03K3/281; H03K3/284
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
114 words
A resettable monostable pulse generator comprising: a charge rundown-timing circuit including a timing capacitor chargeable to a peak level and dischargeable to a predetermined level and a transistor discharge path connected to said timing capacitor; an output pulse generator connected to said charge rundowntiming circuit having one output state when the charge on the timing capacitor is between said peak level and said predetermined level and a second state when the charge on said capacitor is below said predetermined level; and a pair of emitter couple transistors connected so as to sense the voltage level of said timing capacitor and generate an output signal, said output signal being applied to said output pulse generator.
Claim 2
Dependent Claim
114 words
A resettable monostable pulse generator comprising: a charge rundown-timing circuit including a timing capacitor chargeable to a peak level and dischargeable to a predetermined level and a transistor discharge path connected to said timing capacitor; an output pulse generator connected to said charge rundowntiming circuit having one output state when the charge on the timing capacitor is between said peak level and said predetermined level and a second state when the charge on said capacitor is below said predetermined level; and a pair of emitter couple transistors connected so as to sense the voltage level of said timing capacitor and generate an output signal, said output signal being applied to said output pulse generator.
Claim 3
Dependent Claim
25 words
A resettable monostable pulse generator as claimed in claim 1 including a constant amplitude pulse generator connected to the input of said charge rundown-timing circuit.
Claim 4
Dependent Claim
210 words
A resettable monostable generator comprising: a charge rundown-timing circuit including a timing capacitor chargeable to a peak level and dischargeable to a predetermined level; an output pulse generator connected to said charge rundown-timing circuit having one output state when the charge on the timing capacitor is between said peak level and said predetermined level and a second state when the charge on said capacitor is below said predetermined level, said charge rundown-timing circuit comprising: first, second, third and fourth transistors of oNe polarity, a fifth transistor of the opposite polarity, the base of said first transistor connected so as to receive an input pulse, the collector of said first transistor connected to the base of said fifth transistor, emitters of said first and second transmitters connected together and to said output pulse generator, said timing capacitor connected to the base of said third transistor, the base of said third transistor connected to the emitter of said fifth transistor, the emitter of said third transistor connected to the base of said second transistor and the collector of said third transistor connected to the collector of said second transistor, and the collector of said fourth transistor connected to said timing capacitor so as to provide a discharge path for said timing capacitor.
Claim 5
Dependent Claim
210 words
A resettable monostable generator comprising: a charge rundown-timing circuit including a timing capacitor chargeable to a peak level and dischargeable to a predetermined level; an output pulse generator connected to said charge rundown-timing circuit having one output state when the charge on the timing capacitor is between said peak level and said predetermined level and a second state when the charge on said capacitor is below said predetermined level, said charge rundown-timing circuit comprising: first, second, third and fourth transistors of oNe polarity, a fifth transistor of the opposite polarity, the base of said first transistor connected so as to receive an input pulse, the collector of said first transistor connected to the base of said fifth transistor, emitters of said first and second transmitters connected together and to said output pulse generator, said timing capacitor connected to the base of said third transistor, the base of said third transistor connected to the emitter of said fifth transistor, the emitter of said third transistor connected to the base of said second transistor and the collector of said third transistor connected to the collector of said second transistor, and the collector of said fourth transistor connected to said timing capacitor so as to provide a discharge path for said timing capacitor.
Claim 6
Dependent Claim
72 words
A resettable monostable pulse generator as claimed in claim 3 wherein said output pulse generator includes first and second transistors, the base of said first transistor connected to the emitters of said first and second transistor of said charge rundown-timing circuit, the emitters of said first and second transistors connected together and through a resistor to a negative voltage source, and the collector of said first transistor connected to an output terminal.
Claim 7
Dependent Claim
30 words
A resettable monostable pulse generator as claimed in claim 4 wherein said charge rundown-timing circuit includes a plurality of diodes connected between the base of said first transistor and ground.
Claim 8
Dependent Claim
30 words
A resettable monostable pulse generator as claimed in claim 5 wherein said charge rundown-timing circuit includes a diode connected between the collector of said fifth transistor and said timing capacitor.
Claim 9
Dependent Claim
29 words
A resettable monostable pulse generator as claimed in claim 6 including a constant amplitude pulse generator connected to the input of said first transistor of said charge rundown-timining circuit.
Claim 10
Dependent Claim
171 words
A resettable monostable pulse generator responsive to an input pulse comprising a timing capacitor, means for charging the timing capacitor only in response to the input pulse, a constant impedance path for discharging the timing capacitor after it has been charged in response to the pulse, a difference amplifier including a pair of transistors with a common emitter connection, a first of said transistors having a base responsive to the input pulse and the second transistor having a base responsive to the charge level of the capacitor, means for back biasing the first transistor while the capacitor is discharging and for forward biasing the first transistor in response to said pulse, and means responsive to the level of voltage derived at the common connection for deriving an output signal having first and second levels, said first level being derived in response to the voltage having a value greater than a predetermined amplitude and the second level being derived in response to the voltage having a value less than the predetermined amplitude.
Claim 11
Dependent Claim
171 words
A resettable monostable pulse generator responsive to an input pulse comprising a timing capacitor, means for charging the timing capacitor only in response to the input pulse, a constant impedance path for discharging the timing capacitor after it has been charged in response to the pulse, a difference amplifier including a pair of transistors with a common emitter connection, a first of said transistors having a base responsive to the input pulse and the second transistor having a base responsive to the charge level of the capacitor, means for back biasing the first transistor while the capacitor is discharging and for forward biasing the first transistor in response to said pulse, and means responsive to the level of voltage derived at the common connection for deriving an output signal having first and second levels, said first level being derived in response to the voltage having a value greater than a predetermined amplitude and the second level being derived in response to the voltage having a value less than the predetermined amplitude.
Claim 12
Dependent Claim
39 words
The pulse generator of claim 8 wherein the charging means includes switch means responsive to the bias state of the first transistor, said switch means being closed to charge the capacitor only while the first transistor is forward biased.
Claim 13
Dependent Claim
46 words
The pulse generator of claim 9 wherein the charging means further includes diode means connected between the switch means and the capacitor for enabling the capacitor to be charged and for preventing discharge of the capacitor through a path in parallel with the constant impedance path.
Claim 14
Dependent Claim
17 words
The generator of claim 8 wherein the biasing means includes an impedance connected to the common connection.
Claim 15
Dependent Claim
171 words
A resettable monostable pulse generator responsive to an input pulse comprising a timing capacitor, means for charging the timing capacitor in response to the input pulse, a constant impedance path for discharging the timing capacitor after it has been charged in response to the pulse, a difference amplifier having first and second input terminals and an output terminal for Deriving a voltage indicative of the difference between the voltages applied to the first and second input terminals, means for applying the input pulse to one of said input terminals, means for deriving a signal indicative of the current in the constant impedance path, means for feeding said signal to said second input terminal, and means responsive to the voltage derived at the output terminal for deriving an output signal having a first level in response to the voltage at the output terminal having a value greater than a predetermined amplitude and a second level in response to the voltage at the output terminal having a value less than the predetermined amplitude.
Claim 16
Dependent Claim
171 words
A resettable monostable pulse generator responsive to an input pulse comprising a timing capacitor, means for charging the timing capacitor in response to the input pulse, a constant impedance path for discharging the timing capacitor after it has been charged in response to the pulse, a difference amplifier having first and second input terminals and an output terminal for Deriving a voltage indicative of the difference between the voltages applied to the first and second input terminals, means for applying the input pulse to one of said input terminals, means for deriving a signal indicative of the current in the constant impedance path, means for feeding said signal to said second input terminal, and means responsive to the voltage derived at the output terminal for deriving an output signal having a first level in response to the voltage at the output terminal having a value greater than a predetermined amplitude and a second level in response to the voltage at the output terminal having a value less than the predetermined amplitude.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-03-08 | 1974-09-07 | 1975-03-09 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-03-08 | 1978-09-07 | 1979-03-09 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-03-08 | 1982-09-07 | 1983-03-09 | $7700.00 | Window Closed / Lapsed |