Patent US3573633A successfully refreshed from Google Patents.
US3573633A
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Tone burst to frequency generator
Assignee: United States Department of the Navy
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Filing: 1969-05-26
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Granted: 1971-04-06
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Expires: 1989-05-26
Abstract
Abstract A flip-flop chain having feedback connections is arranged to measure one period of the carrier frequency of a tone burst signal. The output of the flip-flop chain gates a submultiple of a clock frequency into a count-up counter during the measured period. A countdown counter is arranged to count at clock frequency. Each time the countdown counter counts through zero, the count stored in the count-up counter is read out nondestructively into the countdown counter which simultaneously sends an output signal to a flip-flop. The divided and shaped output from the flip-flop is a continuous measure of the tone burst carrier frequency.
Inventors
- 👤 Michael T Marrero
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 15:40
CPC Classifications
H; H03; H03B; H03B21/00; H03B21/01; H03B21/02; H03B21/025
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
92 words
In a tone burst to frequency converter, an up-counter, a down-counter, a clock pulse source, means for causing said upcounter to count up at one-half the frequency of said clock pulse source for the duration of one period of said tone burst signal, means for causing said down-counter to count down at said clock pulse frequency, means for transferring the count stored in said up-counter to said down-counter when said down-counter counts to zero, and means for generating a system output signal in response to alternate output signals from said countdown counter.
Claim 2
Dependent Claim
92 words
In a tone burst to frequency converter, an up-counter, a down-counter, a clock pulse source, means for causing said upcounter to count up at one-half the frequency of said clock pulse source for the duration of one period of said tone burst signal, means for causing said down-counter to count down at said clock pulse frequency, means for transferring the count stored in said up-counter to said down-counter when said down-counter counts to zero, and means for generating a system output signal in response to alternate output signals from said countdown counter.
Claim 3
Dependent Claim
60 words
The apparatus of claim 1, wherein said means for causing said up-counter to count-up comprise a chain of flip-flops, means for furnishing a tone burst signal to said chain, means interconnecting the flip-flops of said chain whereby said chain develops an output gating signal having a duration equal to one period of the carrier frequency of said tone burst signal.
Claim 4
Dependent Claim
46 words
The apparatus of claim 2, wherein said means for causing said up-counter to count-up further comprise a counter input gate for gating a divided clock pulse frequency to said up-counter, and means for enabling said counter input gate with said output gating signal from said chain.
Claim 5
Dependent Claim
43 words
The apparatus of claim 3, wherein said means for transferring the count in said up-counter to said down-counter comprise transfer gating means, and means for enabling said transfer gating means with an output signal from said down-counter when said down-counter counts to zero.
Claim 6
Dependent Claim
61 words
The apparatus of claim 4, wherein said means for generating a system output signal comprise an output flip-flop, means connecting the toggle input of said output flip-flop to receive a signal when said down-counter counts to zero, said output flip-flop developing an output signal having a period equal to the measured period of the carrier frequency of said tone burst signal.
Claim 7
Dependent Claim
53 words
The apparatus of claim 5, wherein said chain of flip-flops comprise a first flip-flop, a second flip-flop, and a third flip-flop, said output gating signal being an output from said third flip-flop, and said means for furnishing a tone burst to said chain being connected to the toggle input of said second flip-flop.
Claim 8
Dependent Claim
72 words
The apparatus of claim 6, wherein said means interconnecting said flip-flops comprise a first gate and a second gate, said first gate having an output connected to the set input of said third flip-flop, said second gate having an output connected to the reset input of said third flip-flop, and connecting means whereby said first flip-flop and said second flip-flop control said gates to thereby control the state of said third flip-flop.
Claim 9
Dependent Claim
100 words
The apparatus of claim 7, wherein said connecting means comprise a connection between the 1 output of said first flip-flop to one input of said first gate, a connection between the 1 output of said second flip-flop to a second input of said first gate, a connection between the O output of said first flip-flop to one input of said second gate, a connection between the O output of said second flip-flop to a second input of said second gate, and a feedback connection between the O output of said third flip-flop and thE reset input of said first flip-flop.
Claim 10
Dependent Claim
22 words
The apparatus of claim 8, and including reset means for setting said first flip-flop, and resetting said second flip-flop and said up-counter.
Claim 11
Dependent Claim
39 words
The apparatus of claim 9, wherein said means for causing said up-counter to count-up further comprise a flip-flop connected between the output of said clock source and the input of said counter input gate, for dividing said clock frequency.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-04-05 | 1974-10-05 | 1975-04-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-04-05 | 1978-10-05 | 1979-04-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-04-05 | 1982-10-05 | 1983-04-06 | $7700.00 | Window Closed / Lapsed |