Radiation detection system with automatic sample counting rate determination

Claim 2

A radiation analysis system as set forth in claim 1, including readout means connected to the output of said division means.

Claim 3

A system as set forth in claim 3, wherein said readout means includes display means for continuously indicating the sample count rate computed by said division means.

Claim 4

A radiation analysis system, comprising: detection means for detecting radiation from a radioactive sample; pulse counting registering means for registering the decay events occuring in said sample and detected by said detection means during an elapsed detection time interval; timer register means for counting up thE time elapsed during said detection time interval; and division means for automatically continuously and nondestructively dividing the counts registered by said counting register means by said time elapsed as registered by said timer register means, whereby sample count rate is automatically and continuously determined on line without affecting the stored information regarding elapsed detection time and total decay events detected during said elapsed time period.

Claim 5

A radiation analysis system as set forth in claim 5, including means for automatically compensating the sample count rate computed by said division means for background count rate.

Claim 6

A system as set forth in claim 5, wherein said division means includes: a backward counting dividend register means having a plurality of decades; a transfer means for nondestructively transferring all of the count information in said counting register means to said dividend register means; a second timer register means which is forward counting, said second timer register means having the same decade arrangement as said first timer register means; a quotient register means which is forward counting, said quotient register means having a plurality of decades; first means for simultaneously decrementing said dividend register means while incrementing said second timer register means until said second timer register means registers the same number as said first timer register means, and second means for resetting said second timer register means to zero when said first timer register means and said second timer register means are equal, and to tally a 1 in said quotient register means only if said dividend register means has not gone negative.

Claim 7

A system as set forth in claim 7, wherein said backward counting dividend register means is a backward counting ring circuit configuration for enabling end around counting from a higher order decade to a lower order decade.

Claim 8

A system as set forth in claim 7 and further including: third means, responsive to said dividend register means going negative, for restoring the number in said dividend register means to the last positive remainder which existed when said second timer register means is zero in value; and fourth means for automatically shifting incrementing and decrementing to higher and lower order decades in said dividend register means and said second timer register means while preserving proper decade tally positions in said quotient register means to compensate for said shifting. 10 In a radiation analysis system for automatically computing online sample counting rate activity, the combination comprising: a backward counting dividend register having a plurality of decades, said decades being connected in a ring configuration facilitating selective end around counting from normally higher decades to normally lower order decades; means for selectively inserting into said dividend register a number corresponding to the number of sample counts measured during an elapsed detection time interval; means for detecting the negative state of said dividend register; a first forward counting timer register for counting up the time elapsed during said detection time interval, said first timer register having a plurality of decades; a second forward counting timer register, said second timer register having the same decade arrangement as said first timer register; comparator means for comparing the number in said second timer register with the number in said first timer register as said second timer register is counted up; a forward counting quotient register, said quotient register having a plurality of decades; means for simultaneously decrementing said dividend register while incrementing said second timer register until said comparator means indicates that the numbers in said first timer register and said second timer register are the same; means for resetting said second timer rEgister to zero when said comparator means indicates that the numbers in said first timer register and said second timer register are the same, and to tally a 1 in said quotient register, provided said divided register has not gone negative as indicated by said means for detecting the negative state of said dividend register; means responsive to said dividend register going negative for restoring the number in said dividend register to the last positive remainder which existed when said second timer register was in its last zero state; means for automatically shifting the incrementing and decrementing of said dividend register and said second timer register to higher and lower order decades while simultaneously preserving the proper tally position in said quotient register to compensate for such shifting in said dividend and said second timer registers; and readout means coupled to said quotient register for continuously indicating the sample count rate computed.

Claim 9

A combination as set forth in claim 10, including means for selectively inserting the complement of background count rate into said quotient register prior to initiation of any incrementing of said second timer register and decrementing of said dividend register, whereby the sample count rate computed is automatically compensated for background count rate.