Patent US3579104A successfully refreshed from Google Patents.
US3579104A
Expired / Lapsed
US
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Digital phase meter with compensating means for asymmetric waveform distortion
Assignee: International Standard Electric Corp
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Filing: 1969-04-21
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Granted: 1971-05-18
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Expires: 1989-04-21
Abstract
Abstract A phase-measuring instrument for waves of the same frequency is shown in basic form, in which a digital phase shift (or phase delay) reading is obtained and which may be precalibrated to read numerically in degrees or fractional parts of degrees or radians. A short, basic timing (clock) pulse is first generated every time interval To, and these are counted down also to form an enabling gate of very long duration compared to To. A coincidence circuit generates a phase delay gate equal in duration to the time between positive-going zero crossovers of two waveforms of the same frequency to be measured. This phase delay gate and the aforementioned basic timing pulses and enabling gates are supplied to the three inputs of a coincidence circuit which operate to pass said timing pulses in bursts equal in duration to said phase delay gates, only when all three of said coincidence circuit inputs are present. A counter then evaluates each of said bursts, providing said digital readout. In more sophisticated form, the device takes an average reading between positive-going edges for half of a measurement cycle and between negative-going edges for the other half measurement cycle. Also included as refinements are circuits for avoiding erroneous reading in cases of such severe wave distortion that the positive half wave of the first wave begins before, but ends after, the positive half wave of the second wave.
Inventors
- 👤 Jean Pignard
- 👤 Bernard Wintz
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 10:44
CPC Classifications
G; G01; G01R; G01R25/00; H; H03; H03M; H03M1/00; H03M1/12; H03M1/50; Y; Y10; Y10S; Y10S367/00; Y10S367/901
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
223 words
A digital phase meter for measuring phase difference between first and second periodic input waves of the same frequency, comprising: comparison means responsive to said first and second input waves for generating a phase delay gate for each cycle of said waves, equal in duration to the difference in time between a predetermined point on said first wave and a corresponding point on said second wave; means for generating a continuous series of timing pulses of repetition frequency large compared to the frequency of said waves to be measured; an enabling gate generator interconnected with said means for generating timing pulses for producing enable gating pulses relatively long in duration and equal to a predetermined integral number of pulse repetition intervals of said timing pulses, and further equal in duration to at least one cycle of said first and second waves; pulse control responsive to said timing pulses, said enable gate pulses and said phase delay gates for passing said timing pulses in burst during such time as said timing pulses, enable gate pulses, and phase delay gates are all extant at said pulses control means; and digital counting means for counting pulses within said bursts during each enable gate, thereby to provide a digital number indicative of the phase shift of said second input wave with respect to said first input wave.
Claim 2
Dependent Claim
223 words
A digital phase meter for measuring phase difference between first and second periodic input waves of the same frequency, comprising: comparison means responsive to said first and second input waves for generating a phase delay gate for each cycle of said waves, equal in duration to the difference in time between a predetermined point on said first wave and a corresponding point on said second wave; means for generating a continuous series of timing pulses of repetition frequency large compared to the frequency of said waves to be measured; an enabling gate generator interconnected with said means for generating timing pulses for producing enable gating pulses relatively long in duration and equal to a predetermined integral number of pulse repetition intervals of said timing pulses, and further equal in duration to at least one cycle of said first and second waves; pulse control responsive to said timing pulses, said enable gate pulses and said phase delay gates for passing said timing pulses in burst during such time as said timing pulses, enable gate pulses, and phase delay gates are all extant at said pulses control means; and digital counting means for counting pulses within said bursts during each enable gate, thereby to provide a digital number indicative of the phase shift of said second input wave with respect to said first input wave.
Claim 3
Dependent Claim
26 words
The invention set forth in claim 1, wherein said predetermined points on said first and second input waves are defined as their positive-going zero crossover points.
Claim 4
Dependent Claim
106 words
The invention set forth in claim 2, further defined in that said enable gate generator includes means to generate a switching signal which is in a first switching condition substantially during the first half of said enable gating pulses and which is in a second switching condition substantially during the second half of said enable gating pulses, and said comparison circuit includes means responsive to said switching signals for enabling the generation of said phase delay gates from said first and second input wave positive-going zero crossover points during said first switching condition, and between their respective negative-going zero crossover points during said second switching condition.
Claim 5
Dependent Claim
48 words
The invention set forth in claim 3 further defined in that said comparison means includes means for converting said first and second input waves into corresponding first and second auxiliary waves of standarized amplitude and duration, each equal to the positive half cycle of the corresponding input wave.
Claim 6
Dependent Claim
52 words
The invention se forth in claim 3 further defined in that said comparison means also includes an error detection circuit for providing an indication of erroneous reading comprising logic circuit means for determining whether or not the first occurring positive-going edge, and if not to disable the output of said comparison means.
Claim 7
Dependent Claim
55 words
The invention set forth in claim 5 further defined in that said digital counting means includes means for generating a disabling signal when the register of said counting means registers other than 1 in its hundreds digit, and further means are included for applying said register disabling signal to the output of said error detector.
References Cited (Backward Citations)
US3209254A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-05-17 | 1974-11-16 | 1975-05-18 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-05-17 | 1978-11-16 | 1979-05-18 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-05-17 | 1982-11-16 | 1983-05-18 | $7700.00 | Window Closed / Lapsed |