Electronic display system

Claim 2

An electronic display system comprising: a. a plurality of indicator tubes provided in a predetermined spatial arrangement dependent upon information to be displayed, each of said indicator tubes comprising a gas-filled envelope, one common anode and a plurality of cathodes disposed therein, said cathodes being shaped in the form of characters suitable to represent the respective information elements of said information, each of said indicator tubes being responsive to a relatively high operating potential supplied between the cathode and the anode thereof for effecting a glow-discharge; b. a plurality of common conductors for connecting the cathodes of identical forms of character of said indicator tubes with each other; c. a plurality of first electronic switching means connected with said plurality of common conductors respectively, each of said first switching means having a control electrode for controlling the potential of each of said cathodes in accordance with a first control signal; d. a shift register having a feedback means connected between an output terminal and an input terminal thereof for storing binary signals of the information to be displayed, said binary signals being shifted by at least one clock pulse having a predetermined cyclic period, thereby said binary signals are caused to be circulated in said shift register; e. a gate circuit connected with said shift register for reading out said binary signals stored in said shift register, said gate circuit being controlled by a timing pulse in synchronism with said clock pulse; f. a decoder circuit connected with said gate circuit for supplying said first control signal to the control electrode of said first switching means in accordance with said binary signals passing through said gate circuit; g. a power source means for supplying said operating potential to the anode of each of said indicator tubes; and h. means for distributing said operating potential from said power source means to the anode of each indicator tube in synchronism with said timing pulse, said distributing means being connected between said power source means and the respective anodes.

Claim 3

An electronic display system as set forth in claim 1, wherein said distributing means is composed of a plurality of second electronic switching means, each of said second switching means being connected with the anode of each indicator tube and operated by a second control signal in synchronism with said timing pulse.

Claim 4

An electronic display system as set forth in claim 1, wherein the cathodes of the indicator tubes are shaped in the forms of the numerals ''''0'''' to ''''9,'''' and said indicator tubes are so arranged as to display numerical information.

Claim 5

An electronic display system as set forth in claim 1, wherein memory elements are connected with the gate circuit, thereby effectively applying said first control signal to the control electrodes of said first switching means.

Claim 6

An electronic display system as set forth in claim 4, wherein the memory elements are composed of insulated gate-type field-effect transistors.

Claim 7

An electronic display system as set forth in claim 1, wherein memory elements are connected with the decoder circuit, thereby effectively applying said first control signal to the control electrodes of said first switching means.

Claim 8

An electronic display system as set forth in claim 6, wherein the memory elements are composed of insulated gate-type field-effect transiStors.

Claim 9

An electronic display system as set forth in claim 1, wherein said shift register and said gate circuit are composed of insulated gate-type field-effect transistors.

Claim 10

An electronic display system comprising: a. a plurality of indicator devices each having a common anode electrode and a plurality of cathode electrodes; b. means for connecting corresponding cathode electrodes of said indicator devices to each other; c. first switching means having first control terminals for causing one group of said cathodes connected together to have a first predetermined electrical potential in response to a first control signal supplied to said first control terminals thereof; d. second switching means connected to each of said anodes and having second control terminals for causing different ones of said anodes selectively to receive a second predetermined electrical potential in sequence in response to a second control signal supplied to said second control terminals thereof; e. an N bit shift register for storing N bit binary signals therein, the number N being not less than 4, said binary signals being shifted by at least one clock pulse, comprising a first N-4 bit shift register for storing N-4 bit binary signals, a second 4 bit shift register for storing 4 bit binary signals series-connected with said first shift register, said second shift register comprising 4 unit bit circuits, each unit bit circuit including at least 4 insulated-gate-type field-effect transistors, and feedback means connected between an output of said second shift register and an input of said first shift register; f. means for reading and memorizing said 4 bit binary signals stored in said second shift register comprising a first and a second group of 4 insulated-gate-type field-effect transistors, each transistor of said groups having a control electrode and a first and a second output electrode, means connecting a voltage supply source between said first and second output electrodes of of each transistor of said first group, means connecting each of said control electrodes of said first group of transistors with each of said second output electrodes of said second group of transistors, respectively, means supplying a timing pulse signal to said control electrodes of said second group of transistors, said timing pulse signal being in synchronism with said clock pulse signal in said N bit shift register and said second control signal in said second switching means, and means coupling each of said first output electrodes of said second group of transistors with each of said unit bit circuits of said second shift register, respectively; and g. decoder means for decoding said binary signals into decimal signals coupled between said first control terminals of said first switching means and said reading out and memorizing means.

Claim 11

An electronic display system comprising: a. a plurality of indicator devices each having a common anode electrode and a plurality of cathode electrodes; b. means for connecting corresponding cathode electrodes of said indicator devices to each other; c. first switching means having first control terminals for causing one group of said cathodes connected together to have a first predetermined electrical potential in response to a first control signal supplied to said first control terminals thereof; d. second switching means connected to each of said anodes and having second control terminals for causing different ones of said anodes selectively to receive a second predetermined electrical potential in sequence in response to a second control signal supplied to said second control terminals thereof; e. an N bit shift register for storing N bit binary signals therein, the number N being not less than 4, said binary signals being shifted by at least one clock pulse, comprising a first N-4 bit shift register for storing N-4 bit binary signals, a second 4 bit shift register for storing 4 bit binary signals series-connected with said first shift register, said second shift register comprising 4 unit bit circuits, each unit bit circuit including at least 4 insulated-gate-type field-effect transistors, and feedback means connected between an output of said second shift register and an input of said first shift register; f. means for reading and memorizing said 4 bit binary signals stored in said second shift register comprising a first and a second group of 4 insulated-gate-type field-effect transistors, each transistor of said groups having a control electrode and a first and a second output electrode, means connecting a voltage supply source between said first and second output electrodes of of each transistor of said first group, means connecting each of said control electrodes of said first group of transistors with each of said second output electrodes of said second group of transistors, respectively, means supplying a timing pulse signal to said control electrodes of said second group of transistors, said timing pulse signal being in synchronism with said clock pulse signal in said N bit shift register and said second control signal in said second switching means, and means coupling each of said first output electrodes of said second group of transistors with each of said unit bit circuits of said second shift register, respectively; and g. decoder means for decoding said binary signals into decimal signals coupled between said first control terminals of said first switching means and said reading out and memorizing means.

Claim 12

The electronic display system according to claim 9, wherein said timing pulse signal has a cyclic period of 4 times that of said clock pulse.

Claim 13

The combination comprising: a. an N bit shift register for storing N bit binary signals therein, the number of N being not less than 4, comprising a first N-4 bit shift register for storing N-4 bit binary signals therein said first shift register having an input terminal and an output terminal, and a second 4 bit shift register for storing 4 bit binary signals therein, said second shift register comprising: first, second, third and fourth unit circuits, each unit circuit comprising first, second, third and fourth insulated-gate-type field-effect transistors, each transistor having a first control terminal and first and second output terminals, means connecting said second output terminal of said first transistor with said first control terminal of said second transistor, means connecting said second output terminal of said second transistor with said first output terminal of said Third transistor, means connecting said second output terminal of said third transistor with said first control terminal of said fourth transistor, and means maintaining the potential of said first output terminals of said second and fourth transistors to a reference potential, means connecting the first output terminals of the first transistors in said second, third and fourth unit circuits with the second output terminals of the fourth transistors in said first, second and third unit circuits, respectively; means supplying a first clock pulse signal to the first control terminal of the first transistor in each of said unit circuits; means supplying a second clock pulse signal to the first control terminal of the third transistor in each of said unit circuits, said second clock pulse signal being out of time phase with said first clock pulse signal and having the same cyclic period as said first clock pulse; a first voltage supply source; and first load impedance means respectively connected between said first voltage supply source and the second output terminals of the second and fourth transistors in each of said unit circuit; b. means connecting said first output terminal of said first transistor in said first unit circuit constructing said second shift register with said output terminal of said first shift register; c. feedback means connected between said second output terminal of said fourth transistor in said fourth unit circuit constructing said second shift register and said input terminal of said first shift register; d. a gate circuit comprising: fifth, sixth, seventh and eighth insulated-gate-type field-effect transistors, each transistor having a second control terminal and third and fourth output terminals; means connecting the third output terminals of said fifth, sixth, seventh and eighth transistors with said first, second, third and fourth unit circuits in order to read out said binary signals stored therein, respectively; and means supplying a timing pulse signal to said second control terminals of said fifth, sixth, seventh and eighth transistors, said timing pulse signal being in synchronism with said first clock pulse signal; and e. a memory circuit comprising: ninth, tenth, eleventh and twelfth insulated-gate-type field-effect transistors, each transistor having a third control terminal and fifth and sixth output terminals; means connecting said third control terminals of said ninth, tenth, eleventh and twelfth transistors with said fourth output terminals of said fifth, sixth, seventh and eighth transistors, respectively; means maintaining the potential of said fifth output terminals of said ninth, tenth, eleventh and twelfth transistors to the reference potential; a second voltage source; and second load impedance means respectively connected between said second voltage supply source and said sixth output terminals of said ninth, tenth, eleventh and twelfth transistors.

Claim 14

The combination comprising: a. an N bit shift register for storing N bit binary signals therein, the number of N being not less than 4, comprising a first N-4 bit shift register for storing N-4 bit binary signals therein said first shift register having an input terminal and an output terminal, and a second 4 bit shift register for storing 4 bit binary signals therein, said second shift register comprising: first, second, third and fourth unit circuits, each unit circuit comprising first, second, third and fourth insulated-gate-type field-effect transistors, each transistor having a first control terminal and first and second output terminals, means connecting said second output terminal of said first transistor with said first control terminal of said second transistor, means connecting said second output terminal of said second transistor with said first output terminal of said Third transistor, means connecting said second output terminal of said third transistor with said first control terminal of said fourth transistor, and means maintaining the potential of said first output terminals of said second and fourth transistors to a reference potential, means connecting the first output terminals of the first transistors in said second, third and fourth unit circuits with the second output terminals of the fourth transistors in said first, second and third unit circuits, respectively; means supplying a first clock pulse signal to the first control terminal of the first transistor in each of said unit circuits; means supplying a second clock pulse signal to the first control terminal of the third transistor in each of said unit circuits, said second clock pulse signal being out of time phase with said first clock pulse signal and having the same cyclic period as said first clock pulse; a first voltage supply source; and first load impedance means respectively connected between said first voltage supply source and the second output terminals of the second and fourth transistors in each of said unit circuit; b. means connecting said first output terminal of said first transistor in said first unit circuit constructing said second shift register with said output terminal of said first shift register; c. feedback means connected between said second output terminal of said fourth transistor in said fourth unit circuit constructing said second shift register and said input terminal of said first shift register; d. a gate circuit comprising: fifth, sixth, seventh and eighth insulated-gate-type field-effect transistors, each transistor having a second control terminal and third and fourth output terminals; means connecting the third output terminals of said fifth, sixth, seventh and eighth transistors with said first, second, third and fourth unit circuits in order to read out said binary signals stored therein, respectively; and means supplying a timing pulse signal to said second control terminals of said fifth, sixth, seventh and eighth transistors, said timing pulse signal being in synchronism with said first clock pulse signal; and e. a memory circuit comprising: ninth, tenth, eleventh and twelfth insulated-gate-type field-effect transistors, each transistor having a third control terminal and fifth and sixth output terminals; means connecting said third control terminals of said ninth, tenth, eleventh and twelfth transistors with said fourth output terminals of said fifth, sixth, seventh and eighth transistors, respectively; means maintaining the potential of said fifth output terminals of said ninth, tenth, eleventh and twelfth transistors to the reference potential; a second voltage source; and second load impedance means respectively connected between said second voltage supply source and said sixth output terminals of said ninth, tenth, eleventh and twelfth transistors.

Claim 15

The combination defined in claim 11, wherein each of said first and second load impedance means comprises an insulated-gate-type field-effect transistor having a gate, source and drain electrodes, said gate electrode being connected with said drain electrode.

Claim 16

The combination defined in claim 11, wherein said means connecting the third output terminals of said fifth, sixth, seventh and eighth transistors with said first, second, third and fourth unit circuits comprises connecting said third output terminals with said second output terminals of said fourth transistors in said first, second, third and fourth unit circuits, respectively.

Claim 17

The combination defined in claim 11, wherein said timing pulse signal has a cyclic period of 4 times as long as said first clock pulse signal.