Patent US3582636A successfully refreshed from Google Patents.
US3582636A
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US
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Circuit arrangement for calculating a check digit
Assignee: US Philips Corp
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Filing: 1968-12-24
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Granted: 1971-06-01
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Expires: 1988-12-24
Abstract
Abstract A circuit for calculating and employing a check digit, having two module M counters, the first counter coupled directly to a weighted series of pulses, the second counter responsive to a carry from the first counter for counting double the number of input pulses applied to the first counter, completion of the series providing the M complement of the check digit in said second counter, and providing the check digit to the circuit resulting in nonzero condition in the second counter of the digit sequence is in error.
Inventors
- 👤 Uwe Bertram
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 15:57
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/08; G06F11/10; G06F11/1008; G06F11/1012; G06F11/104
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
168 words
A circuit arrangement for calculating a check digit from a plurality of digits for data control by means of weighted transverse sums in accordance with the relation: Wherein Zi designates the digits, m the number of digits, i the place of the digit, P the check digit, Man integer having no common factors with the possible values of Gi and Zi, and Gi the weights arithmetically arrayed in dependence upon the place in the descending sequence of the natural numbers, comprising first and second mod M counters, first means introducing each of said weighted digits in pulse form in descending sequence to said first counter, second means introducing each of said digits in weighted form, for summation as digits pulses, in descending sequence to said second counter, and third means responsive to a carry signal from said first counter for doubling the input pulses to said second counter, the state of said second counter after introduction of all of said plurality of digits representative of said check digit.
Claim 2
Dependent Claim
168 words
A circuit arrangement for calculating a check digit from a plurality of digits for data control by means of weighted transverse sums in accordance with the relation: Wherein Zi designates the digits, m the number of digits, i the place of the digit, P the check digit, Man integer having no common factors with the possible values of Gi and Zi, and Gi the weights arithmetically arrayed in dependence upon the place in the descending sequence of the natural numbers, comprising first and second mod M counters, first means introducing each of said weighted digits in pulse form in descending sequence to said first counter, second means introducing each of said digits in weighted form, for summation as digits pulses, in descending sequence to said second counter, and third means responsive to a carry signal from said first counter for doubling the input pulses to said second counter, the state of said second counter after introduction of all of said plurality of digits representative of said check digit.
Claim 3
Dependent Claim
116 words
The combination of claim 1 wherein said circuit arrangement provides an indication of erroneous digit transmission of said plurality of digits with said check digit, said circuit arrangement including a switch in said second means, said switch being in an open position, said first means for introducing each of said digits in weighted form for summation as pulses in descending sequence to said first counter said check digit submitted last, said second counter counting pulses only at said double rate upon activation of said third means, the state of said second counter after introduction of all of said plurality of digits including said check digit indicating a state of 0 mod M for error free transmission.
Claim 4
Dependent Claim
26 words
A circuit arrangement as claimed in claim 1 wherein said check digit P is the complement of the resultant position of the second mod M counter.
Claim 5
Dependent Claim
92 words
A circuit arrangement as claimed in claim 1 wherein the carry signal of the first counter sets a bistable trigger, the output of said bistable trigger being connected to one input of an AND gate, the other input of said AND gate receiving input pulses from said first means the output of said AND gate being connected through an OR gate to the counting input of said second counter, said second means applying said input pulses through a second input of said OR gate to the counting input of said second counter.
Claim 6
Dependent Claim
62 words
A circuit arrangement as claimed in claim 4 wherein said second means includes a switch which is open at the check of a digit sequence already provided with a check digit and in that said second mod M counter delivers an error signal, if it has not reached its 0-position after complete writing of a digit sequence provided with said check digit.
Claim 7
Independent Claim
146 words
A method of calculating a check digit from a plurality of digits and using said check digit to check accuracy of transmission of said plurality of digits, each of said digits represented by a plurality of pulses, in descending order of significance, comprising the steps of counting in a module M counter said pulses in accordance with the relationship (m+1).Zi+M.Z2+(m-1).Z3+...2.Zm M-P mod M wherein m is the number of digits in said plurality, Z is the digit in descending order of significance, M is the module of said counter, and P is the check digit, said counter at the completion of said count providing an indication of said check digit P, and counting in said counter a transmitted plurality of said digits including said check digit in accordance with the relationship (m+1).Z1+m.Z2+(m-1).Z3+...2.Zm+P wherein a resultant of other than 0 mod M indicates error in said transmission.
Claim 8
Independent Claim
146 words
A method of calculating a check digit from a plurality of digits and using said check digit to check accuracy of transmission of said plurality of digits, each of said digits represented by a plurality of pulses, in descending order of significance, comprising the steps of counting in a module M counter said pulses in accordance with the relationship (m+1).Zi+M.Z2+(m-1).Z3+...2.Zm M-P mod M wherein m is the number of digits in said plurality, Z is the digit in descending order of significance, M is the module of said counter, and P is the check digit, said counter at the completion of said count providing an indication of said check digit P, and counting in said counter a transmitted plurality of said digits including said check digit in accordance with the relationship (m+1).Z1+m.Z2+(m-1).Z3+...2.Zm+P wherein a resultant of other than 0 mod M indicates error in said transmission.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-05-31 | 1974-11-30 | 1975-06-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-05-31 | 1978-11-30 | 1979-06-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-05-31 | 1982-11-30 | 1983-06-01 | $7700.00 | Window Closed / Lapsed |