Transistor
Abstract
Abstract A high-power transistor in which the emitter is in the form of a grid adjoining a surface of a semiconductor body having collector and base regions, the latter surrounding the emitter. The apertures in the emitter grid form a plurality of juxtaposed rows with the base region. The surface of the semiconductor body is covered with an insulating layer which covers the line of intersection of the emitter base junction with the surface. Base and emitter contacts are provided on the insulating layer forming an interdigital system. Viewed along a row, the apertures in the emitter grid first have an increasing width and then a decreasing width. The apertures in a direction at right angles to the row correspond to digits of the base contact are arranged in rows. The insulating layer also comprises windows located substantially between four adjacent apertures through which the emitter contacts are connected to the emitter region.
Inventors
- 👤 George Kerr
Bibliographic Details
Claims Analysis
Total Claims: 2References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1974-05-31 | 1974-11-30 | 1975-06-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1978-05-31 | 1978-11-30 | 1979-06-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1982-05-31 | 1982-11-30 | 1983-06-01 | $7700.00 | Window Closed / Lapsed |