Amplifier circuits

Claim 2

An amplifier circuit comprising, a. first and second transistors of the same conductivity each having a base, collector and emitter electrode, b. a resistive voltage divider coupled between the base electrode of said first transistor and a point of reference potential, and further including a DC coupling path between another point on said voltage divider and the base electrode of said second transistor, c. means coupled between the emitter electrode of said second transistor and a point of reference potential for providing a current return path, d. means coupled to said collector electrodes of said first and second transistors and said voltage divider for applying an operating potential thereto, and e. a resistor coupling said emitter electrode of said first transistor to said emitter electrode of said second transistor, said resistor providing a DC voltage thereacross equal to the DC voltage drop between said base electrode of said first transistor and said other point on said voltage divider in accordance with the application of said operating potential, whereby said bias on said first transistor is substantially equal to said bias on said second transistor.

Claim 3

An amplifier circuit comprising, a. first and second transistors of the same conductivity each having a base, collector and emitter electrode, b. a voltage divider including first and second series resistors coupled between the base electrode of said first transistor and a point of reference potential, and further including a DC coupling path between the junction of said first and second resistors and the base electrode of said second transistor, c. means coupled between said emitter electrode of said second transistor and a point of reference potential for providing a current return path, d. means coupled to said collector electrode of said first and second transistors and said voltage divider for applying an operating potential thereto, and e. a third resistor coupling said emitter electrode of said first transistor to said emitter electrode of said second transistor, said third resistor provide a DC voltage thereacross substantially equal to the DC voltage across said first resistor in accordance with the application of said operating potential.

Claim 4

An amplifier circuit comprising, a. first and second transistors of the same conductivity each having a base, collector and emitter electrode, b. a voltage divider including first and second series resistors coupled between the base electrode of said first transistor and a point of reference potential, and further including a DC coupling path between the junction of said first and second resistors and the base electrode of said second transistor, c. means coupled between said emitter electrode of said second transistor and a point of reference potential for providing a current return path, d. means coupled to said collector electrode of said first and second transistors and said voltage divider for applying an operating potential thereto, and e. a third resistor coupling said emitter electrode of said first transistor to said emitter electrode of said second transistor, said third resistor provide a DC voltage thereacross substantially equal to the DC voltage across said first resistor in accordance with the application of said operating potential.

Claim 5

An amplifier circuit, comprising, a. a first transistor having a base, collector and emitter output electrode arranged in an emitter follower configuration, b. first and second resistors in a series path between said emitter output electrode and a point of reference potential, c. second and third transistors of the same conductivity, each having a base, collector and emitter electrode, said base electrode of said second transistor coupled to said emitter output electrode of said first transistor and said base electrode of said third transistor coupled between the junction of said first and second resistors, d. a third resistor coupled between the emitter electrodes of said second and third transistors, said third resistor beIng of a magnitude to provide a DC voltage drop thereacross substantially equal to any DC voltage drop across said first resistor, e. means coupled to the emitter electrode of said third transistor for providing a ground return path for said second and third transistors for all current flowing through the collector to emitter path of said second and third transistors.

Claim 6

An amplifier circuit, comprising, a. a first transistor having a base, collector and emitter output electrode arranged in an emitter follower configuration, b. first and second resistors in a series path between said emitter output electrode and a point of reference potential, c. second and third transistors of the same conductivity, each having a base, collector and emitter electrode, said base electrode of said second transistor coupled to said emitter output electrode of said first transistor and said base electrode of said third transistor coupled between the junction of said first and second resistors, d. a third resistor coupled between the emitter electrodes of said second and third transistors, said third resistor beIng of a magnitude to provide a DC voltage drop thereacross substantially equal to any DC voltage drop across said first resistor, e. means coupled to the emitter electrode of said third transistor for providing a ground return path for said second and third transistors for all current flowing through the collector to emitter path of said second and third transistors.

Claim 7

A circuit arrangement for amplifying signals comprising, a. a first amplifier having an input and output terminal, said amplifier including means for applying signals to said input terminal, b. first means coupled to said output terminal of said amplifier for providing a load impedance for DC and signal currents, c. a second amplifier having an input, output and common terminal, a direct coupling path between said input terminal of said second amplifier and said output terminal of said first amplifier, d. a third amplifier having an input, output and common terminal, said input terminal of said third amplifier direct coupled to a point on said first means, e. a resistive impedance coupled between the output terminals of said second and third amplifiers, said resistive impedance providing a DC voltage drop thereacross substantially equal to any DC voltage difference between said input terminals of said second and third amplifiers, as coupled to said load impedance means, f. second means including another resistor coupling said output terminal of said third amplifier to said common terminal, said second means operating to bypass all current flowing in said second and third amplifiers due to any DC and signal components flowing therethrough to said common terminal, said means as coupled, further causing any voltage due to signal current components developed across said resistive impedance to provide degeneration for signals applied to said input electrode of said second amplifier, while further serving, with said first means, to maintain the biasing of said second and third amplifiers relatively equal.

Claim 8

A circuit arrangement for amplifying signals comprising, a. a first amplifier having an input and output terminal, said amplifier including means for applying signals to said input terminal, b. first means coupled to said output terminal of said amplifier for providing a load impedance for DC and signal currents, c. a second amplifier having an input, output and common terminal, a direct coupling path between said input terminal of said second amplifier and said output terminal of said first amplifier, d. a third amplifier having an input, output and common terminal, said input terminal of said third amplifier direct coupled to a point on said first means, e. a resistive impedance coupled between the output terminals of said second and third amplifiers, said resistive impedance providing a DC voltage drop thereacross substantially equal to any DC voltage difference between said input terminals of said second and third amplifiers, as coupled to said load impedance means, f. second means including another resistor coupling said output terminal of said third amplifier to said common terminal, said second means operating to bypass all current flowing in said second and third amplifiers due to any DC and signal components flowing therethrough to said common terminal, said means as coupled, further causing any voltage due to signal current components developed across said resistive impedance to provide degeneration for signals applied to said input electrode of said second amplifier, while further serving, with said first means, to maintain the biasing of said second and third amplifiers relatively equal.

Claim 9

An amplifier circuit for use in a color television receiver of the type employing chrominance processing circuitry for selectively amplifying chrominance subcarrier signal frequencies including an oscillatory burst signal transmitted with a composite television signal during a color transmission, comprising: a. first, second and third terminals, b. a resistive divider coupled between said first terminal and said third terminal, c. a first and second transistor of the same conductivity each having a base, collector and emitter electrode, a first direct coupling path between said first terminal and said base electrode of said first transistor, and a second direct coupling path between a point on said resistive divider and said base electrode of said second transistor, a third direct coupling path between said emitter electrode of said second transistor and said second terminal, d. a resistor coupling said emitter electrode of said first transistor to said second terminal, said resistor selected in accordance with the magnitude of the resistance appearing between said first terminal and the base electrode of said second transistor, for developing a DC potential thereacross equal to any DC potential difference between said first terminal and said base electrode of said second transistor, and e. means, coupled between said second and third terminals for providing a current return path for all currents both AC and DC which flow through the collector to emitter paths of said first and second transistors, whereby said first and second transistors are biased at relatively the same DC level, f. means coupled between said first and third terminals for applying said chrominance subcarrier signal frequencies including said oscillatory burst signal thereto, to cause said first transistor to linearly operate, as biased, with a given gain for said chrominance subcarrier signal frequencies, and said second amplifier, as biased, To operate linearly for said burst signal with a larger gain than said given gain.

Claim 10

An amplifier circuit for use in a color television receiver of the type employing chrominance processing circuitry for selectively amplifying chrominance subcarrier signal frequencies including an oscillatory burst signal transmitted with a composite television signal during a color transmission, comprising: a. first, second and third terminals, b. a resistive divider coupled between said first terminal and said third terminal, c. a first and second transistor of the same conductivity each having a base, collector and emitter electrode, a first direct coupling path between said first terminal and said base electrode of said first transistor, and a second direct coupling path between a point on said resistive divider and said base electrode of said second transistor, a third direct coupling path between said emitter electrode of said second transistor and said second terminal, d. a resistor coupling said emitter electrode of said first transistor to said second terminal, said resistor selected in accordance with the magnitude of the resistance appearing between said first terminal and the base electrode of said second transistor, for developing a DC potential thereacross equal to any DC potential difference between said first terminal and said base electrode of said second transistor, and e. means, coupled between said second and third terminals for providing a current return path for all currents both AC and DC which flow through the collector to emitter paths of said first and second transistors, whereby said first and second transistors are biased at relatively the same DC level, f. means coupled between said first and third terminals for applying said chrominance subcarrier signal frequencies including said oscillatory burst signal thereto, to cause said first transistor to linearly operate, as biased, with a given gain for said chrominance subcarrier signal frequencies, and said second amplifier, as biased, To operate linearly for said burst signal with a larger gain than said given gain.

Claim 11

The amplifier circuit according to claim 5 further comprising, a. means, including a first selective network, coupled to the collector electrode of said first transistor for providing further selectivity to said chrominance subcarrier frequency signals as applied between said first and third terminals.

Claim 12

The amplifier circuit according to claim 5 further comprising, a. means, including a second selective, network coupled to the collector electrode of said second transistor for providing frequency selectivity to said oscillatory burst signal as oscillatory burst signal as linearly amplified by said second transistor.

Claim 13

The amplifier according to claim 5 further comprising, a. a first switchable differential amplifier including third and fourth transistors having their emitter electrodes coupled to said collector electrode of said first transistor, b. means including a first selective network coupled to said collector electrode of said fourth transistor for providing further selectivity to said chrominance subcarrier frequency signals as applied between said first and third terminals, c. a second switchable differential amplifier including fifth and sixth transistors having their emitter electrodes coupled to said collector electrode of said second transistor, d. means, including a second selective network coupled to the collector electrode of said sixth transistor for providing frequency selectivity to said oscillatory burst signal as linearly amplified by said second transistor e. a common biasing network coupled to the base electrodes of said fourth and fifth transistors for supplying operating bias to said first and second switchable differential amplifiers, f. means coupled to the base electrodes of said third and sixth transistors for alternatively switching between said first and second differential amplifiers according to the period of said oscillatory burst signal, to cause said fourth transistor of said first differential amplifier to be switched off and said fifth transistor of said second differential amplifier to be switched on during the presence of said burst signal.

Claim 14

An amplifier for use in a color television receiver of the type employing chrominance processing circuitry for selectively amplifying chrominance subcarrier signal frequencies including an oscillatory burst signal transmitted with a composite television signal during a color transmission, comprising, a. a monolithic circuit chip having an array of chip terminals incorporating, b. a follower transistor amplifier configuration including a direct coupling path between the base electrode thereof and said chrominance processing amplifier, said follower amplifier including a resistive impedance load connected in series between said emitter electrode and a point of reference potential, c. a second transistor amplifier, including a direct coupling path between the base electrode of said second transistor and the emitter electrode of said follower transistor, d. a third transistor amplifier including a direct coupling path between the base electrode thereof and a point of said resistive load connected in series with the emitter electrode of said follower transistor, a DC coupling path between the emitter electrode of said third transistor and one of said chip terminals, e. a resistor coupling said emitter electrode of said first transistor to said one chip terminal, said resistor being of a magnitude to provide a DC voltage thereacross equal to the DC voltage difference between said emitter electrode of said follower transistor and said point on said resistive load, and f. an off-chip network, including a shunt resistor and capacitor, coupled between said chip terminal and a point of reference potential for providing a common current return path for said second and third transistor amplifiers for both DC and signal cOmponents flowing therethrough, for operating with said resistor to bias said second transistor amplifier in a linear region for chrominance subcarrier signal frequencies and for operating to bias said third transistor in a linear region for said oscillatory burst signal.

Claim 15

An amplifier for use in a color television receiver of the type employing chrominance processing circuitry for selectively amplifying chrominance subcarrier signal frequencies including an oscillatory burst signal transmitted with a composite television signal during a color transmission, comprising, a. a monolithic circuit chip having an array of chip terminals incorporating, b. a follower transistor amplifier configuration including a direct coupling path between the base electrode thereof and said chrominance processing amplifier, said follower amplifier including a resistive impedance load connected in series between said emitter electrode and a point of reference potential, c. a second transistor amplifier, including a direct coupling path between the base electrode of said second transistor and the emitter electrode of said follower transistor, d. a third transistor amplifier including a direct coupling path between the base electrode thereof and a point of said resistive load connected in series with the emitter electrode of said follower transistor, a DC coupling path between the emitter electrode of said third transistor and one of said chip terminals, e. a resistor coupling said emitter electrode of said first transistor to said one chip terminal, said resistor being of a magnitude to provide a DC voltage thereacross equal to the DC voltage difference between said emitter electrode of said follower transistor and said point on said resistive load, and f. an off-chip network, including a shunt resistor and capacitor, coupled between said chip terminal and a point of reference potential for providing a common current return path for said second and third transistor amplifiers for both DC and signal cOmponents flowing therethrough, for operating with said resistor to bias said second transistor amplifier in a linear region for chrominance subcarrier signal frequencies and for operating to bias said third transistor in a linear region for said oscillatory burst signal.

Claim 16

The amplifier according to claim 1, further comprising: a. means for applying signals to said base electrodes of said first and second transistors to cause said resistor to degenerate said signals as applied to the base electrode of said first transistor and to therefore operate said first transistor at a lower gain than said second transistors.