Sequential timing system

Claim 2

A sequential timing system comprising: first switching means for supplying a first current path for a first electrical signal upon being actuated; first timing means connected to receive said first electrical signal and for being instantaneously actuated for a fixed predetermined maximum period of time upon receipt of said signal; second switching means electrically connected to said first timing means for supplying a current path for a second electrical signal upon said first timing means being actuated; second timing means connected to receive said second electrical signal and for providing a time delayed actuation in response to receipt of said second electrical signal; third switching means electrically connected to said second timing means for supplying a third current path for a third electrical signal upon said timing means being actuated; and fourth switching means connected to receive a command signal for inhibiting said first, second and third current paths.

Claim 3

A sequential timing system according to claim 1 wherein: said first switching means further includes a first and second pole; and an impedance electrically connecting said first and second poles.

Claim 4

A sequential timing system according to claim 2 wherein said first timing means further comprises: a varying voltage divider network receiving said first electrical signal and providing a varying voltage output; a first transistor having a base, emitter and collector, said base receiving said first varying voltage output for initially rendering said first transistor conductive; and a second transistor operatively connected to said first transistor and being biased into a conducting state upon said first transistor becoming conductive.

Claim 5

A sequential timing system according to claim 3 further comprising: said first transistor is an NPN-type; said second transistor is a PNP-type; and said varying voltage divider network includes a resistor and capacitor connected in series.

Claim 6

A sequential timing system according to claim 4 wherein said second switching means further comprises: a third transistor including an emitter, collector and base for providing a current path from said emitter to said collector; and a resistor connected between said emitter and base for providing a bias voltage to said third transistor upon said second transistor becoming conductive.

Claim 7

A timing syStem comprising: timing means for instantaneously providing an output signal for a fixed predetermined maximum period of time upon receipt of a first electrical signal having a varying voltage divider network receiving said first electrical signal and providing a varying output, a first transistor having a base, emitter and collector receiving said varying voltage for initially rendering said first transistor conductive, and a second transistor operatively connected to said first transistor for providing said output signal upon said first transistor becoming conductive; and switching means having a third transistor including an emitter, collector and base connected to receive said output signal for providing a current path from said emitter to said collector for a second electrical signal upon receipt of said output signal and to inhibit said second electrical signal in the absence of said output signal and a resistor connected between said emitter and base for providing a bias voltage to said third transistor upon said second transistor becoming conductive.

Claim 8

A timing syStem comprising: timing means for instantaneously providing an output signal for a fixed predetermined maximum period of time upon receipt of a first electrical signal having a varying voltage divider network receiving said first electrical signal and providing a varying output, a first transistor having a base, emitter and collector receiving said varying voltage for initially rendering said first transistor conductive, and a second transistor operatively connected to said first transistor for providing said output signal upon said first transistor becoming conductive; and switching means having a third transistor including an emitter, collector and base connected to receive said output signal for providing a current path from said emitter to said collector for a second electrical signal upon receipt of said output signal and to inhibit said second electrical signal in the absence of said output signal and a resistor connected between said emitter and base for providing a bias voltage to said third transistor upon said second transistor becoming conductive.

Claim 9

A timing system comprising: timing means for providing a current path after a fixed predetermined period of time having a varying voltage divider network connected to receive a first electrical signal and providing an output voltage that varies as a function of time, a first transistor having a base, emitter and collector receiving said output voltage for initially rendering said first transistor conductive and for further rendering said first transistor nonconductive upon said output voltage exceeding a predetermined magnitude after a fixed period of time, a second transistor operatively connected to said first transistor for being biased into a conducting state when said first transistor becomes conductive and becoming nonconductive when said first transistor becomes nonconductive and a third transistor operatively connected to said second transistor for being biased into a nonconducting state when said second transistor becomes conductive and for being biased into a conducting state when said second transistor becomes noncunductive; and switching means having a first input connected to said third transistor and a second output connected to receive a second electrical signal for providing a current path to said second electrical signal upon said third transistor being conductive.

Claim 10

A timing system comprising: timing means for providing a current path after a fixed predetermined period of time having a varying voltage divider network connected to receive a first electrical signal and providing an output voltage that varies as a function of time, a first transistor having a base, emitter and collector receiving said output voltage for initially rendering said first transistor conductive and for further rendering said first transistor nonconductive upon said output voltage exceeding a predetermined magnitude after a fixed period of time, a second transistor operatively connected to said first transistor for being biased into a conducting state when said first transistor becomes conductive and becoming nonconductive when said first transistor becomes nonconductive and a third transistor operatively connected to said second transistor for being biased into a nonconducting state when said second transistor becomes conductive and for being biased into a conducting state when said second transistor becomes noncunductive; and switching means having a first input connected to said third transistor and a second output connected to receive a second electrical signal for providing a current path to said second electrical signal upon said third transistor being conductive.

Claim 11

A timing system according to claim 7 wherein said switching means further comprises: transistor means including a Darlington circuit connected to receive a second electrical signal and for providing a current path for said second electrical signal; and a resistor connected to said transistor means for providing a bias voltage to said transistor means upon said third transistor being conductive.