Adjustable cycle length pseudorandom sequence generator

Claim 2

In a pseudorandom sequence generator including a shift register responsive to a clock pulse for shifting data through the register, the improvement which comprises: A. a counter having a settable counting cycle and providing a control output on reaching a selected count. B. means for setting said counter to count through said selected count; C. means for applying clock pulses to said register; and D. means responsive to the counter control output for inhibiting the shifting of data through the register when said counter has counted through said selected count.

Claim 3

A pseudorandom sequence generator according to claim 1 in which the counter setting means comprises a plurality of selectable switches connected to said counter for selecting the count through which said counter is to count.

Claim 4

generates a second control signal derived from said first control signal when the counter is in the R counting state, said second control signal resetting said generator and said counter.

Claim 5

generates a second control signal derived from said first control signal when the counter is in the R counting state, said second control signal resetting said generator and said counter.

Claim 6

means for energizing the timing gate associated with a selected counter unit only when each of the preceding counter units has advanced to its maximum count;

Claim 7

means for energizing the timing gate associated with a selected counter unit only when each of the preceding counter units has advanced to its maximum count;

Claim 8

means for generating a control output in response to the state of said counter units when said units have advanced to a state corresponding to a selected count; and

Claim 9

means for generating a control output in response to the state of said counter units when said units have advanced to a state corresponding to a selected count; and

Claim 10

A pseudorandom sequence generator according to claim 1 in which said register comprises an n-bit feedback shift register for generating a string of pseudorandom outputs when said counter has counted through a count less than said selected count, said register terminating said string in response to said control output when said counter has counted through a count equal to said selected count.

Claim 11

A pseudorandom sequence generator according to claim 3 which includes means for setting said register to a predetermined number sequence on terminating said string.

Claim 12

means for terminating said count and loading a number corresponding to said selected value into said counter after sAid state has been reached.

Claim 13

means for terminating said count and loading a number corresponding to said selected value into said counter after sAid state has been reached.

Claim 14

A pseudorandom sequence generator having an adjustable cycle length, said generator comprising A. a counter having a counting cycle length which is selectable over a selected counting range and providing a control output indicative of the selected count; B. means for selecting the count through which said counter is to count; C. means responsive to the control output of said counter for generating a continuous string of pseudorandom sequences whenever the count in said counter is less than said selected value and for initiating a new string whenever said count equals said selected value, whereby the length of said string is determined by the setting of said counter; and D. means for applying clock pulses to said counter and to said generator to step said counter and said generator through their sequential operating states.

Claim 15

A pseudorandom sequence generator having an adjustable cycle length, said generator comprising A. a counter having a counting cycle length which is selectable over a selected counting range and providing a control output indicative of the selected count; B. means for selecting the count through which said counter is to count; C. means responsive to the control output of said counter for generating a continuous string of pseudorandom sequences whenever the count in said counter is less than said selected value and for initiating a new string whenever said count equals said selected value, whereby the length of said string is determined by the setting of said counter; and D. means for applying clock pulses to said counter and to said generator to step said counter and said generator through their sequential operating states.

Claim 16

A pseudorandom sequence generator according to claim 5 in which said counter provides a count whose length is substantially continuously adjustable over the entire counting range of the counter.

Claim 17

A pseudorandom sequence generator according to claim 5 in which said counter comprises A. a plurality of counter units connected in series; and B. control means for controlling the counting cycle and comprising

Claim 18

A pseudorandom sequence generator according to claim 7 in which the ''''n'''' s complement of the selected value is loaded into the counter units during the loading interval, where ''''n'''' is the maximum count to which each counter unit counts, and in which the count termination and loading sequence is initiated when the lowest order counter unit arrives at a counting state of n- 1 while each of the higher order counters is in a counting state of ''''n'''' and is completed when said lowest order unit arrives at a counting state of ''''n.''''

Claim 19

A pseudorandom sequence generator according to claim 7 in which said counter is arranged to provide a count whose maximum magnitude is at least one unit greater than the maximum magnitude of the count nominally provided by the counter units alone one said switch means whereby the count to which each said counter unit is to count may be selected by setting said switch means.

Claim 20

A pseudorandom sequence generator according to claim 9 in which said switch means are continuously adjustable over the range of the selected count.

Claim 21

A pseudorandom sequence generator according to claim 5 in which said counter includes a plurality of counter units connected in series, each counter unit being connected to at least one said switch means whereby the count to which each said counter unit is to count may be selected by setting said switch means.

Claim 22

A pseudorandom sequence generator according to claim 5 which includes means for setting said generator to a selected state when a new string is initiated whereby the initial digits in each said string form a usable number sequence.

Claim 23

Apparatus for generating a pseudorandom sequence of selectable cycle length, comprising A. a pseudorandom sequence generator connected to provide as outputs a sequence of digits, one at a time; B. a counter connected to count to a selected number corresponding to the number of digits which are to comprise a given sequence; C. means for setting the counter to count to said selected number; and D. means responsive to the count in said counter for resetting said generator and said counter when said counter has counted through the selected count.

Claim 24

Apparatus for generating a pseudorandom sequence of selectable cycle length, comprising A. a pseudorandom sequence generator connected to provide as outputs a sequence of digits, one at a time; B. a counter connected to count to a selected number corresponding to the number of digits which are to comprise a given sequence; C. means for setting the counter to count to said selected number; and D. means responsive to the count in said counter for resetting said generator and said counter when said counter has counted through the selected count.

Claim 25

Apparatus according to claim 13 which include means for selecting an initial sequence to which said generator is to be reset.

Claim 26

Apparatus according to claim 14 in which the means for setting said counter comprises a plurality of settable switches, each of which are manipulable to set the count to any one of a plurality of counts.

Claim 27

Apparatus according to claim 13 in which A. said counter loads the selected number in ''''R'''' s complement form and generates said count by successively passing through the states R-N to R, where R is the highest counting state of said counter; and B. the means responsive to the count in the counter