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US3649850A Expired / Lapsed US ⏱️ 0.0 years remaining

Crystal-controlled square wave generator

Assignee: AT&T Inc
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Filing: 1969-11-26
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Granted: 1972-03-14
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Expires: 1989-11-26
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Abstract

Abstract A crystal, a wideband noninverting amplifier with low input and output impedance, a nonphase-shifting limiter circuit, a level shift and buffer output stage provide a square wave voltage output with a high degree of stability. The crystal is connected in a feedback circuit between the output of the limiter circuit and the input of the amplifier. The limiter circuit contains a pair of emitter-coupled transistors neither one of which is driven into saturation. Cutoff of each of the transistors in the pair provides clipping of the sinusoidal voltage peaks provided at the input of the limiter circuit. The generator contains only transistors, resistors, and a piezoelectric crystal, and is therefore especially suited for integrated circuit use.

Inventors

  • 👤 Paul C Davis

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-28 13:28
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/26; H03K3/28; H03K3/281; H03K3/282; H03K3/283

Claims Analysis

Total Claims: 4
Claim 1
Independent Claim 278 words
Apparatus for limiting the peaks of a voltage waveform having a DC voltage component comprising first and second transistors each having base, emitter, and collector electrodes, first and second impedance means equal in value and series connected between the emitter electrodes of said first and second transistors, a DC voltage source, means for connecting said DC voltage source to the collector electrode of said first transistor, a constant current source connected to the junction of said first and second impedances, means for coupling said voltage waveform having a DC voltage component to the base electrode of said first transistor, a source of DC potential connected to the base electrode of said second transistor and equal in value to said DC voltage component, a third impedance means connected between the collector electrode of said second transistor and said DC voltage source, and means for coupling to an output the voltage waveform generated across said third impedance means; wherein said constant current source includes a third transistor having its collector electrode connected to the junction of said first and second impedance means, its emitter electrode connected through a fourth impedance means to ground potential, and its base electrode connected to a DC reference potential which forward-biases its base-emitter junction; and wherein said source of DC potential connected to the base electrode of said second transistor includes a fourth transistor having its collector electrode connected both to the base of said second transistor and through a fifth impedance means to said DC voltage source, its emitter electrode connected through a sixth impedance means to said ground potential, and its base electrode directly connected to the base electrode of said third transistor.
Claim 2
Dependent Claim 278 words
Apparatus for limiting the peaks of a voltage waveform having a DC voltage component comprising first and second transistors each having base, emitter, and collector electrodes, first and second impedance means equal in value and series connected between the emitter electrodes of said first and second transistors, a DC voltage source, means for connecting said DC voltage source to the collector electrode of said first transistor, a constant current source connected to the junction of said first and second impedances, means for coupling said voltage waveform having a DC voltage component to the base electrode of said first transistor, a source of DC potential connected to the base electrode of said second transistor and equal in value to said DC voltage component, a third impedance means connected between the collector electrode of said second transistor and said DC voltage source, and means for coupling to an output the voltage waveform generated across said third impedance means; wherein said constant current source includes a third transistor having its collector electrode connected to the junction of said first and second impedance means, its emitter electrode connected through a fourth impedance means to ground potential, and its base electrode connected to a DC reference potential which forward-biases its base-emitter junction; and wherein said source of DC potential connected to the base electrode of said second transistor includes a fourth transistor having its collector electrode connected both to the base of said second transistor and through a fifth impedance means to said DC voltage source, its emitter electrode connected through a sixth impedance means to said ground potential, and its base electrode directly connected to the base electrode of said third transistor.
Claim 3
Dependent Claim 291 words
A crystal-controlled square wave generator comprising a piezoelectric crystal, an amplifier-limiter means having an input and output for providing at its output an amplified peak-clipped replica of a sinusoidal current provided to its input, means for establishing a feedback loop including said crystal between said input and output whereby oscillations are maintained at a frequency substantially equal to the series resonant frequency of said crystal, means for amplifying and further clipping the voltage waveform provided at the output of said amplifier-limiter means, said amplifier-limiter means including a pair of emitter-coupled transistors each one of which is biased to be in the active region for a range of values on both sides of the point of inflection in said sinusoidal current and is cut off by alternate peaks of said sinusoidal current, said amplifier-limiter means further including transistor means for amplifying said sinusoidal current to provide an amplified sinusoidal voltage with a DC voltage component, means for coupling said sinusoidal voltage to a base electrode of one of said pair of emitter-coupled transistors, means for providing a DC potential equal to said DC voltage component to a base electrode of the other one of said pair of emitter-coupled transistors, said transistor means for amplifying said sinusoidal current including a first transistor having its emitter and collector electrodes connected through first and second impedances respectively to opposite terminals of a DC voltage source, and said means for providing a DC potential to a base electrode of the other one of said pair of emitter-coupled transistors including a second transistor having its base electrode connected to the base electrode of said first transistor and its emitter and collector electrodes connected through third and fourth impedances respectively to opposite terminals of said DC voltage source.
Claim 4
Dependent Claim 291 words
A crystal-controlled square wave generator comprising a piezoelectric crystal, an amplifier-limiter means having an input and output for providing at its output an amplified peak-clipped replica of a sinusoidal current provided to its input, means for establishing a feedback loop including said crystal between said input and output whereby oscillations are maintained at a frequency substantially equal to the series resonant frequency of said crystal, means for amplifying and further clipping the voltage waveform provided at the output of said amplifier-limiter means, said amplifier-limiter means including a pair of emitter-coupled transistors each one of which is biased to be in the active region for a range of values on both sides of the point of inflection in said sinusoidal current and is cut off by alternate peaks of said sinusoidal current, said amplifier-limiter means further including transistor means for amplifying said sinusoidal current to provide an amplified sinusoidal voltage with a DC voltage component, means for coupling said sinusoidal voltage to a base electrode of one of said pair of emitter-coupled transistors, means for providing a DC potential equal to said DC voltage component to a base electrode of the other one of said pair of emitter-coupled transistors, said transistor means for amplifying said sinusoidal current including a first transistor having its emitter and collector electrodes connected through first and second impedances respectively to opposite terminals of a DC voltage source, and said means for providing a DC potential to a base electrode of the other one of said pair of emitter-coupled transistors including a second transistor having its base electrode connected to the base electrode of said first transistor and its emitter and collector electrodes connected through third and fourth impedances respectively to opposite terminals of said DC voltage source.

References Cited (Backward Citations)

US2863048A Cited
US3078377A Cited
US3134947A Cited
US3259761A Cited
US3378790A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1975-03-14 1975-09-13 1976-03-14 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1979-03-14 1979-09-13 1980-03-14 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1983-03-14 1983-09-13 1984-03-14 $7700.00 Window Closed / Lapsed

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