Information output system

Claim 2

An information output system for use with a visual numerical display device having a plurality of digit display positions, said system providing for suppressing unnecessary zeros in the digit display positions of the display device exceeding the most significant digit of the number to be displayed, and comprising: a first shift register having a plurality of information storing stages for registering numerical information in a first format; means coupled to said first shift register for circulation of said numerical information therethrough in accordance with desired timing of shift; a second shift register having a corresponding plurality of information storing stages for registering numerical information in a second format, said numerical information in said second shift register being shifted therethrough as a function of the timing of the shift of said first shift register means; means coupled to said first register for responding to the numerical information of the first format circulating therein, for storing numerical information of the second format in each stage of the second register as to which the respectively corresponding stage of the first register contains numerical information identifying a non-zero digit of the number to be displayed; means responsive to the numerical information of the second format shifting through said second shift register for developing in said second shift register numerical information in the second format indicative of all digit positions of the number to be displayed; and output means responsive to the numerical information in said first register and to the numerical digit position information developed in said second shift register, for producing a visual display of only so much of said numerical information circulating in said first shift register as identifies significant digits of the number to be displayed, and thereby to suppress display of undesired zeros in the digit positions of the display exceeding the most significant digit of the number to be displayed.

Claim 3

The information output system according to claim 1, further including: means for establishing in said visual display the position of a decimal point in the number identified by the numerical information in said first shift register, further comprising: counter means for storing the number of decimal places of a number to be displayed and identified by the numerical information in said first shift register; means for adjusting the count in said counter means in synchronism with the shifting of said second shift register; and means responsive to a predetermined count of said counter means for controlling said developing means to develop numerical information of the second format indicative of digit positions to be displayed in accordance with the decimal point position in the number identified by the numerical information of said first shift register.

Claim 4

An information output system as recited in claim 1 wherein said first format is a plural bit coded digital format including a number of groups of coded digital bits corresponding to the number of digit positions of the display and identifying the digit in each position of the display, and said second format is a single bit digital format, and wherein: each stage of said first register includes a number of bit storage elements corresponding to the number of coded bits for a single digit, and said means for developing numerical information of the second format in said second shift register is connected to predetermined ones of said bit storage elements of said first register for responding to each grouP of coded bits, in succession, to determine if a non-zero digit is identified thereby, and further is connected to a predetermined stage of said second register to insert a bit therein for each said group of coded bits identifying a non-zero digit, simultaneously with the circulation of the bits of each such group into the storage elements of the stage of said first register corresponding to said predetermined stage of the second register.

Claim 5

The information output system according to claim 3 wherein each of said digit storage stages of said first register comprises a plurality of bit storage elements of like number, connected serially for circulation of all bits of all groups therethrough simultaneously and in succession.

Claim 6

The information output system according to claim 3 wherein each of said storing stages of said second shift register comprises a single bit storage element.

Claim 7

A numerical information output system for use with a visual numerical display device having a plurality of digit display positions, said system providing for suppressing unnecessary zeros in the digit display positions of the display device exceeding the most significant digit of the number to be displayed, and comprising: a first circulating shift register having a plurality of digit storing stages for storing a plurality of digits corresponding to the plurality of digit display positions of the display device, each digit storage stage comprising a predetermined number of bit storage elements for registering a decimal number in accordance with a plural bit code as represented by a pattern of logical states of a group of coded bits for each such digit; means for effecting circulation of the contents of said first register; a second circulating shift register having the same number of storing stages as the number of digit storage stages of said first register, said second register undergoing shift in synchronism with the shift in the first register as to the successive stages thereof; means for sensing the logical state of a digit in a specified digit position of the first register as defined by a group of coded bits for a given digit stored in predetermined ones of the bit storage elements of said first shift register, and for writing said logical state into a specified storing stage of the second register as that group of bits circulates into associated storage elements of the respectively corresponding stage of the first register; means responsive to the logical state written into said specified stage of said second shift register for rewriting that state into a stage of said second register which is one bit position less significant than that of the stage wherein the previously written logical state is stored, to provide in the second register logical state pattern indicative of the digit positions of the decimal number registered in the first register; output means energized in accordance with the decimal number registered in the first register; and means for controlling the output means in accordance with the logical state pattern in the second register.

Claim 8

A numerical information output system for use with a visual numerical display device having a plurality of digit display positions, said system providing for suppressing unnecessary zeros in the digit display positions of the display device exceeding the most significant digit of the number to be displayed, and comprising: a first circulating shift register having a plurality of digit storing stages for storing a plurality of digits corresponding to the plurality of digit display positions of the display device, each digit storage stage comprising a predetermined number of bit storage elements for registering a decimal number in accordance with a plural bit code as represented by a pattern of logical states of a group of coded bits for each such digit; means for effecting circulation of the contents of said first register; a second circulating shift register having the same number of storing stages as the number of digit storage stages of said first register, said second register undergoing shift in synchronism with the shift in the first register as to the successive stages thereof; means for sensing the logical state of a digit in a specified digit position of the first register as defined by a group of coded bits for a given digit stored in predetermined ones of the bit storage elements of said first shift register, and for writing said logical state into a specified storing stage of the second register as that group of bits circulates into associated storage elements of the respectively corresponding stage of the first register; means responsive to the logical state written into said specified stage of said second shift register for rewriting that state into a stage of said second register which is one bit position less significant than that of the stage wherein the previously written logical state is stored, to provide in the second register logical state pattern indicative of the digit positions of the decimal number registered in the first register; output means energized in accordance with the decimal number registered in the first register; and means for controlling the output means in accordance with the logical state pattern in the second register.

Claim 9

A numerical information output system in accordance with claim 6, wherein each storing stage of the second register is a one bit storage element.

Claim 10

A numerical information output system in accordance with claim 6, wherein each storing stage of the second register is constituted of the same predetermined number of plural bit storage elements as each stage of the first register.

Claim 11

A numerical information output system in accordance with claim 6, wherein said specified digit storage stage of the first register is a buffer circuit comprising a plurality of bit storage shift elements of the same predetermined number as the number of elements for each stage of the first shift register, and connected to receive the recirculating output from the last stage of said first shift register.

Claim 12

A numerical information output system in accordance with claim 6, wherein each non-zero digit of a dEcimal number to the displayed is represented by the combination of logics ''''1'''' and ''''0'''' and wherein: said sensing and writing means includes a first logic gate connected to receive the outputs of a predetermined plurality of specified consecutive bit storage elements of the first register and to produce a logic ''''1'''' output whenever any bit of the group of bits stored therein is a logic ''''1'''' bit and writes said logic ''''1'''' into a specified storing stage of the second register at each time when the group of coded bits stored in said specified consecutive bit storage elements to said first register corresponds to an individual digit; and said rewriting means includes a second logic gate connected to receive the output of a given stage of said second shift register and to provide its output to the input of a different stage of said second shift register thereby to rewrite the previously written logic ''''1'''' into a storing stage of said second register which is one bit position less significant with respect to the storing stage wherein the previously written logic ''''1'''' is stored, to provide in the second register a logic ''''1'''' pattern indicative of the digit positions of the decimal number registered in the first register.

Claim 13

A numerical information output system in accordance with claim 10, wherein each stage of said first register includes N storage elements and each stage of said second register includes only a single storage element, which further comprises: means for providing timing pulses, means for supplying the timing pulses to all elements of said first register, the logic bits in the storage elements of said first register being shifted to the respectively next successive storage elements and recirculated in accordance with each successive one of said timing pulses; means for supplying every Nth timing pulse to the storage elements of said second shift register, the logic bits in the storage elements of said second register being shifted as a function of every Nth timing pulse, and said sensing, writing and rewriting means include: a first OR gate receiving as inputs the logical states of the specified consecutive predetermined plurality of bit storage elements of the first register. an AND gate receiving as inputs the logical state output of the bit element next to the least significant bit element of the second register and the complement of the final timing pulse of a group of said pulses equal in number to the number of storage elements of said first register and thus sufficient for making one circulation in the first register, a second OR gate receiving as inputs an output of the first OR gate and an output of the AND gate, and the output of which is supplied to the most significant bit element of the second register, and said gates are operative during repetition of circulation to produce a logic ''''1'''' pattern in the storage elements of the second register corresponding to all digit positions of the decimal number registered in the first register.

Claim 14

A numerical information output system in accordance with claim 10, wherein each stage of said second shift register has a corresponding plurality of digit storage elements as each stage of said first shift register and there is further provided: means for providing timing pulses simultaneously to all bit storage elements of said first and second registers, to logic bits stored in said storage elements of each of said registers being shifted simultaneously to the respectively next successive storage elements and recirculated, in each of said registers in response to successive ones of said timing pulses; and said sensing, writing and rewriting means include: an AND gate receiving as an input the logical state output of the bit storage element next to the least significant bit storage element of the second register and the complement of the final timing pulse of a group of said timing pulses equal in number to the number of storage elements of one of said registers and thus s required for making one circulation in each of said registers, and an OR gate receiving as an input the logical state output of the bit storage element next to the least significant one of the first register and the output of said AND gate, the output of said OR gate being supplied to the input to the most significant bit storage element of the second register.

Claim 15

A numerical information output system in accordance with claim 6, wherein each non-zero digit of a decimal number to be displayed is represented by the combination of logics ''''1'''' and ''''0'''' and wherein: said sensing and writing means includes a first logic gate connected to receive the outputs of specified consecutive bit storage elements of said first register and to produce a logic ''''1'''' output only where no bit of the group of the group of bits stored therein is a logic ''''1'''' bit, and writes the logic ''''1'''', the complement of said no logic ''''1'''', into a specified storing stage of the second register when the group of bits in said specified plurality of bit storage elements of said first register currently represent the digit for the most significant digit position of the display; and said rewriting means includes a second logic gate connected to receive the output of a given stage of said second shift register and to provide its output to the input of a different stage of said second shift register thereby to rewrite the previously written logic ''''1'''' into a storing stage of said second register which is one bit position less significant with respect to the storing stage wherein the previously written logic ''''1'''' is stored, said second gate furthermore receiving the output of said first gate and enabled thereby only when the output of said first gate is a logic ''''1'''', thereby to provide in the second register a logic ''''1'''' pattern indicative of the undesired zeros in the digit positions of the display which are more significant than the most significant digit position of the decimal number registered in the first register; and said controlling means controls the output means in accordance with the logic ''''1'''' pattern in the second register so as to suppress the undesired zeros in the more significant digit positions of the display.

Claim 16

A numerical information output system in accordance with claim 13, wherein each stage of said first register includes N storage elements and each stage of said second register includes only a single storage element, which further comprises: means for providing timing pulses; means for supplying the timing pulses to all elements of said first register, the logic bits in the storage elements of said first register being shifted to the respectively next successive storage elements and recirculated in accordance with each successive one of said timing pulses; means for supplying every Nth timing pulse to the storage elements of said second shift register, the logic bits in the storage elements of said second register being shifted as a function of every Nth timing pulse, and said sensing, writing and rewriting means include: a first OR gate receiving as inputs the logical states of the specified consecutive predetermined plurality of bit storage elements of the first register, an inverter receiving as an input the output of said OR gate, a first AND gate receiving as inputs the output of said inverter and the final timing pulse of a group of said timing pulses equal in number to the number of storage elements of said first register and thus as required for making one circulation in the first register, and a second AND gate receiving as inputs the output of said inverter, the complement of said final timiNg pulse, and the logical state output of the bit storage element next to the least significant bit storage element of the second register, the outputs of both said AND gates being fed to the most significant bit element of the second register, said OR gate, said inverter and said AND gates producing during repetition of circulation a logic ''''1'''' bit pattern in the storage elements of the second register corresponding to all the digit positions of the display which are more significant than the most significant digit of the decimal number registered in the first register.

Claim 17

A numerical information output system as recited in claim 6 wherein there is provided means for establishing in said visual display the position of a decimal point in the number identified by the numerical information in said first shift register, further comprising: counter means for storing the number of decimal places of a number to be displayed and identified by the numerical information in said first shift register; means for adjusting the count in said counter means in synchronism with the shifting of said second shift register; and means responsive to a predetermined count of said counter means for controlling said developing means to develop numerical information of the second format indicative of digit positions to be displayed in accordance with the decimal point position in the number identified by the numerical information of said first shift register.