Recovery of horizontal sync pulses from a composite synchronizing format

Claim 2

A synchronizing signal recovery circuit comprising: an inhibit gate having a first and a second input terminal, said first input terminal being connected to an input source of a composite video synchronizing signal comprising both vertical and horizontal synchronizing pulses, the horizontal synchronizing pulses having a substantially shorter duration than the vertical synchronizing pulses; a delay circuit connected to said input source, said delay circuit having an output terminal connected to said second input terminal; and means for controlling said inhibit gate by counting the same number of horizontal synchronizing pulses in each field supplied by said input source, said means being connected to a first and a second Control terminal of said inhibit gate, and said inhibit gate being activated to gate out the vertical synchronizing pulses present at said first input terminal to substitute delayed horizontal synchronizing pulses from said second input terminal supplied by said delay circuit.

Claim 3

The synchronizing signal recovery circuit of claim 1 wherein said delay circuit has a delay substantially equal to the interval between consecutive horizontal synchronizing pulses.

Claim 4

The synchronizing signal recovery circuit of claim 1 wherein said means for controlling said inhibit gate comprises a pulse generator and a counter reset generator connected to said input source; said pulse generator having a first and a second output terminal, said first output terminal being connected to said first control terminal and said second output terminal being connected to a pulse counter; said pulse counter having another input connected to the output of said counter reset generator to insure that said counter is reset properly; and said first output terminal of said pulse generator being connected to said second control terminal for inhibiting said inhibit gate before the occurrence of a vertical synchronizing pulse to allow the substitution of a horizontal synchronizing pulse from said delay circuit to produce an output signal having horizontal synchronizing pulses substantially equally based.

Claim 5

The synchronizing signal recovery circuit of claim 3 wherein said pulse generator produces a pulse output of a fixed duration for said first output terminal, said second output terminal providing an output pulse which results from gating the output signal of said first output terminal with said input source to produce a counter drive signal having an equal number of horizontal synchronizing pulses in each field of a video frame.

Claim 6

The synchronizing signal recovery circuit of claim 3 wherein said counter reset generator resets said pulse counter by one pulse per field which is dependent upon said pulse counter, and one pulse per frame which is independent of said pulse counter and is produced by gating the output signal of the first output terminal of said pulse generator with said input source.

Claim 7

A synchronizing signal recovery circuit comprising: an input source of a composite video synchronizing signal comprising both vertical and horizontal synchronizing pulses, the horizontal synchronizing pulses having a substantially shorter duration than the vertical synchronizing pulses; a delay circuit connected to said input source having a delay substantially equal to the interval between horizontal pulses, the output of said delay circuit and of said input source being each connected to an input terminal of an inhibit gate having two control terminals and an output; and a pulse generator and a counter reset generator connected to said input source, said pulse generator having two output terminals, one of said two output terminals being connected to one of said control terminals and the other output terminal being connected to a pulse counter, said pulse counter having another input connected to the output of said counter reset generator to insure that said counter is reset properly, the output of said pulse counter being connected to the other of said control terminals for inhibiting said inhibit gate before the occurrence of a vertical synchronizing pulse to allow the substitution of a horizontal synchronizing pulse from said delay circuit to produce an output signal having horizontal synchronizing pulses substantially equally spaced.

Claim 8

A synchronizing signal recovery circuit comprising: an input source of a composite video synchronizing signal comprising both vertical and horizontal synchronizing pulses, the horizontal synchronizing pulses having a substantially shorter duration than the vertical synchronizing pulses; a delay circuit connected to said input source having a delay substantially equal to the interval between horizontal pulses, the output of said delay circuit and of said input source being each connected to an input terminal of an inhibit gate having two control terminals and an output; and a pulse generator and a counter reset generator connected to said input source, said pulse generator having two output terminals, one of said two output terminals being connected to one of said control terminals and the other output terminal being connected to a pulse counter, said pulse counter having another input connected to the output of said counter reset generator to insure that said counter is reset properly, the output of said pulse counter being connected to the other of said control terminals for inhibiting said inhibit gate before the occurrence of a vertical synchronizing pulse to allow the substitution of a horizontal synchronizing pulse from said delay circuit to produce an output signal having horizontal synchronizing pulses substantially equally spaced.